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s6e1c3 series 32- bit arm ? cortex ? - m 0+ fm 0+ microcontroller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134 - 1709 ? 408- 943 - 2600 document number: 002- 00233 rev.*b revised march 4, 2016 the s6e1 c 3 series is a series of highly integrated 32 - bit microcontrollers designed for embedded controllers aiming at low power consumption and low cost . th is s eries has the arm cortex - m0+ processor with on - chip flash memory and sram, and consists of peripheral functions such as various t imers, adc and c ommunication i nterfaces (uart, c sio (spi), i 2 c , i 2 s, smart card, and usb). the products which are described in this data sheet are placed into type 3 - m0+ product categories in "fm 0+ family peripheral manual ". features 32- bit arm cortex - m0+ core ? processor version: r 0 p1 ? maximum operating frequency: 40 .8 mhz ? nested vectored interrupt controller (nvic): 1 nmi (non - maskable interrupt) and 24 peripheral interrupt with 4 selectable interrupt priority levels ? 24- bit system timer (sys t ick): system timer for os task management bit band operation c ompatible with cortex - m3 bit band operation. on - chip memor y ? flash memory ? up to 128 kbyte s ? read cycle: 0 wait - cycle ? security function for code protection ? sram th e on- chip sram of this series has o ne independent sram . ? up to 16 kbytes ? 4kbytes: can retain value in d eep standby mode usb interface usb interface is composed of device and host with main pll, usb clock can be generated by multiplication of main clock. ? usb device ? usb 2.0 full - speed supported ? max 6 endpoint supported ? endpoint 0 is control transfer ? endpoint 1, 2 can be selected bulk - transfer, interrupt - transfer or isochronous - transfer ? endpoint 3 to 5 can select bulk - transfer or interrupt - transfer ? endpoint 1 to 5 comprise double buffer ? the size of each endpoint is according to the follows ? endpoint 0, 2 to 5 : 64 bytes ? endpoint 1 : 256 bytes ? usb host ? usb 2.0 full/low - speed supported ? bulk - transfer, interrupt - transfer and isochronous - transfer support ? usb device connected/disconnected automatically detect ? in/out token handshake packet automatically ? max 256 - byte packet - length supported ? wake - up function supported multi - function s erial i nterface (max 6 channels ) ? 3 channels with 64byte fifo (ch.4, 6 and 7), 3 channels without fifo (ch.0, 1 and 3) ? the operation mode of each channel can be selected from one of the following. ? uart ? csio (csio is known to many customers as spi) ? i 2 c ? uart ? full duplex double buffer ? parity can be enabled or disable d . ? built - in dedicated baud rate generator ? external clock available as a serial clock ? hardware flo w control* : automatically control the transmission by cts/rts (only ch.4) * : s6e1c32b0a/s6e1c31b0a and s6e1c32c0a/s6e1c31c0a do not support hardware flow control. ? various error detection functions (parity errors, framing errors, and overrun errors) ? csio (also known as spi) ? full duplex double buffer ? built - in dedicated baud rate generator ? overrun error detection function ? serial chip select function (ch 1 and ch6 only) ? data length : 5 to 16 bit s ? i 2 c ? standard - mode (max : 100 kbps) supported / fast - mode (max 400 kbps) supported . ? i 2 s (mfs - i2s) ? using csio (max 2 ch: ch.4, ch.6) and i 2 s clock generator ? supports two transfer protocol ? i 2 s ? msb - justified ? master mode only
document number: page of 107 s6e1c3 series i2c slave ? i2c slave supports the slave function of i2c and wake up function from standby mode. descriptor system data transfer contr oller ( dstc ) (64 channels ) ? the dstc can transfer data at high speed without going via the cpu. the dstc adopts the descriptor system and, following the specified contents of the descriptor that has already been constru cted on the memory, can access directly the memory / peripheral device and performs the data transfer operation. ? it supports the software activation, the hardware activation and the chain activation functions a/d converter (max : 8 channels ) ? 12 bit a/d ? successive a pproximation type ? conversion time: s 2.7 v v ? priority conversion available ( 2 levels of priority) ? scan conversion mode ? built in fifo for conversion data storage (for scan conversion: 16 steps, for p riority conversion: 4 steps) base timer (max : 8 channels ) the operation mode of each channel can be selected from one of the following. ? 16 bit pwm timer ? 16 bit ppg timer ? 16/32 bit reload timer ? 16/32 bit pwc timer general - purpose i/o port this series can use its pin as a general purpose i/o port when it is not used for an external bus or a peripheral function. ports can be set to fast general purpose i/o ports or slow general purpose i/o ports. in addition, this series has a port relocate function that can set to which i/o port a peripheral function ca n be allocated. ? all ports are fast gpio which can be accessed by 1cycle ? capable of controlling the pull up of each pin ? capable of reading pin level directly ? ort relocate function ? up to 54 fast general purpose i/o p orts 4 pin p ackage ? certain ports are 5 v tolerant 4 list of functions and 5 /o circuit type for the corresponding pins. dual timer (32 - /16 - bit down counter) the dual timer consists of two programmable 32 /16 bit down counters. the operation mode of each timer channel can be selected from one of the following. ? run ning mode ? periodi mode (= reload mode ) ? shot mode real - time c lock the real time lock count s y ear/ m onth/ d ay/ h our/ m inute/ s econd/ d ay of the week from year year 99. ? the rtc can generate an interrupt at a specific time (y ear/ m onth/ d ay/ h our/ m inute/ s econd/ d ay of the week ) and can also generate an interrupt in a specific year, in a specific month, on a specific day, at a specific hour or at a specific minute. ? it has a timer interrupt function generating an interrupt upon a specific time or at specific intervals. ? it can keep counting while rewriting the time. ? it can count leap years automatically. watch counter the watch ounter wake s up the microcontroller from the low power consumption mode. the clock source can be selected from the main clock, the sub clock, the built in high speed cr clock or the built speed cr clock. interval timer: up to 64 s (s ub lock : 32.768 khz ) external interrupt controller unit ? up to 12 external i nterrupt input pins ? n m askable interrupt (nmi) input pin : 1 watchdog t imer (2 channels ) the watchdog timer generate s an interrupt or a reset when the counter reaches a time out value. this series consists of two different watchdogs, h ardware watchdog and s oftware watchdog. the h ardware watchdog timer is clocked by the built speed cr os cillator. therefore the h ardware watchdog is active in any power consumption modes except rtc, stop, deep standby rtc and deep standby stop mode. crc (cyclic redundancy check) accelerator the crc accelerator calculates the crc which has a heavy softwa re processing load, and achieves a reduction of the integrity check processing load for reception data and storage. ? ccitt crc16 and ieee 802.3 crc32 are supported. ? ccitt crc16 generator polynomial: 0x1021 ? 802.3 crc32 generator polynomial: 0x04c11db7 h dmi - cec/remote control receiver (up to 2 channels) ? cec transmitter ? header block automatic transmission by judging signal free ? generating status interrupt by detecting arbitration lost
document number: page of 107 s6e1c3 series ? generating start, eom, ack automatically to output cec transmission by setting 1 byte data ? generating transmission status interrupt when transmitting 1 block (1 byte data and eom/ack) ? ? automatic ack reply function available ? line error detection function available ? remote control receiver ? 4 bytes reception buffer ? repeat code detection function available smart card interface (max 1 channel) ? compliant with iso7816 3 specification ? card reader only/b class card only ? available protocols ? transmitter: 8e2, 8o2, 8n2 ? receiver: 8e1, 8o1, 8n2, 8n1, 9n1 ? inverse mode ? tx/rx fifo integrated (rx: 16 bytes, tx:16 bytes) clock and reset ? clocks a clock can be selected from five clock sources ( external oscillator s, built oscillator , and m ain pll). ? main lock: 8 mhz to 4 8 ? sub lock : 32.768 khz ? built in high speed lock : 8 ? built speed lock : 100 khz ? main pll lock 8mhz to 16mhz (input), 75mhz to 150mhz (output) ? resets ? reset request from the initx pin ? power on reset ? software reset ? watchdog timer reset ? voltage detection reset ? clock s uper isor reset clock super v isor (csv) the clock supervisor monitors the failure of external clocks with a clock generated by a built cr oscillator. ? if an e xternal clock failure (clock stop) is detected, a reset is asserted. ? if an e xternal frequency anomaly is detected, an interrupt or a reset is asserted. low - voltage detector (lvd) this s eries monitors the voltage on the vcc pin with a 2 stage mechanism. when the voltage falls below a designated voltage, the low voltage detector generates an interrupt or a reset. ? lvd1: monitor v and error reporting via an interrupt ? lvd2: auto reset operation low power consumption m ode this series has six power consumption modes. ? sleep ? timer ? ? stop ? deep standby rtc (selectable between keeping the value of ram and not) ? deep standby stop (selectable between keeping the value of ram and not) peripheral clock gating the system can reduce the current consumption of the total system with gating the operation clocks of peripheral functions not used. debug ? serial wire debug port (sw dp) ? micro trace buffer (mtb) unique id a 41 bit unique value of the device has been set. power supply ? wide voltage range : vcc = 1.65 v to v vcc = 3.0v to 3.6v (when usb is used)
document number: page 4 of 107 s6e1c3 series table of contents features ................................................................................................................................................................................... 1 1. product lineup .................................................................................................................................................................. 6 2. packages ........................................................................................................................................................................... 7 3. pin assignment ................................................................................................................................................................. 8 4. list of pin functions ....................................................................................................................................................... 15 5. i/o circuit type ................................................................................................................................................................ 28 6. handling precautions ..................................................................................................................................................... 33 6.1 precautions for product design precautions for package mounting 34 precautions for use environment 7. handling devices ............................................................................................................................................................ 37 8. block diagram ................................................................................................................................................................. 40 9. memory ma p .................................................................................................................................................................... 41 10. pin status in each cpu state ........................................................................................................................................ 44 11. electrical characteristics ............................................................................................................................................... 47 11.1 absolute maximum ratings 47 11.2 recommended operating conditions 48 11.3 dc characteristics 49 11.3 .1 current rating 49 11.3.2 pin characteristics 54 11.4 ac characteristics 55 11.4.1 main clock input characteristics 55 11.4.2 sub clock input characteristics 56 11.4.3 built cr oscillation characteristics 57 11.4.4 operating conditions of main pll (in the case of using the main clock as the input clock of the pll) 58 11.4.5 operating conditions of main pll (in the case of using the built in high speed cr clock as the input clock of the main pll) 58 11.4.6 reset input characteristics 59 11.4.7 on reset timing 59 11.4.8 base timer input timing 11.4.9 csio/spi/uart timing 61 11.4.10 external input timing 78 11.4.11 c timing / i2c slave timing 79 11.4.12 s timing (mfs i2s timing) 80 11.4.13 smart card interface characteristics 82 11.4.14 dp timing 83 11.5 12 bit a/d converter 84 11 usb characteristics 87 11.7 voltage detection characteristics 92 11.7.1 voltage detection reset 92 11.7.2 voltage detection interrupt 93 11.8 flash memory write/erase characteristics 94 11.9 return time from low power consumption mode 95 11.9.1 return factor: interrupt/wkup 95 11.9.2 return factor: reset 97 12. ordering information ...................................................................................................................................................... 99 13. package dimensions .................................................................................................................................................... 100 document history ............................................................................................................................................................... 106
document number: page 5 of 107 s6e1c3 series sales, sol utions, and legal information ........................................................................................................................... 107
document number: page of 107 s6e1c3 series 1. product lineup memory size product name s6e1c31b0 a / s6e1c31c0 a / s6e1c31d0 a s6e1c32b0 a / s6e1c32c0 a / s6e1c32d0 a on - chip flash memory 64 kbytes 128 kbytes chip 12 kbytes 16 kbytes pin count 48 64 cpu freq uency 40.8 power supply voltage range 1.65 v to v usb2.0 ( /host) 1 unit 64 ch multi function serial interface (uart/csio/i /i2s ) 2 ch. (max) ch.0/3 without 4 ch. (max) ch.0/1/3 without ch. 6 with fifo 6 ch. (max) ch.0/1/3 without ch.4/6/7 with 6 ch. (max) ch.0/1/3 without ch.4/6/7 with i2s : no i2s : 1 ch (max) ch. 6 with fifo i2s : 2 ch (max) ch. 4/6 with fifo base timer (pwc/reload timer/pwm/ppg) 8 ch (max) dual timer 1 unit cec/ remote control 1 h.( ax) ch.1 2 ch (max) ch.0/1 2c slave no 1 ch (max) smart card interface no 1 ch (max) real time clock 1 unit watch counter 1 unit crc accelerator ye s watchdog timer 1 ch. (sw) + 1 ch. (hw) external interrupt 5 pins (max), nmi 1 7 pins (max), nmi x 1 9 pins (max), nmi x 1 12 pins (max) nmi x 1 i/o port 20 pins (max) 24 pins (max) 38 pins (max) 54 pins (max) 12 bit a/d converter 4 ch (1 unit) ch ( 1 unit) 8 ch ( 1 unit) 8 ch. (1 unit) csv (clock super isor) ye s lvd (low oltage detect ) ch. built high speed 8 mhz ( typ ) speed 100 khz ( typ ) debug function unique id ye s note: ? all signals of the peripheral function in each product cannot be allocated by limiting the pins of package. it is necessary to use the port relocate function of the i/o port according to your function use. see " 11 . electrical characteristics 11.4 ac characteristics 11.4.3 built -in cr oscillation characteristics " for accuracy of built - in cr.
document number: page 7 of 107 s6e1c3 series 2. packages product name package s6e1c32 b 0 a (wlcsp) s6e1c32b0 a / s6e1c31b0 a s6e1c32c0 a / s6e1c31c0 a s6e1c32d0 a / s6e1c31d0 a wlcsp (tbd) ? lqfp: (0.80 mm pitch) ? qfn: wnu032 (0.50 mm pitch) ? lqfp: lqa048 (0.50 mm pitch) ? qfn: wny048 (0.50 mm pitch) ? lqfp: lqd064 (0.50 mm pitch) ? qfn: wns064 (0.50 mm pitch) ? ? : available note: ? see " 13 . package dimensions " for detailed information on each package.
document number: page 8 of 107 s6e1c3 series 3. pin assignment lqd064 - 02 (top view) note: ? the number after the underscore ("_") in a pin name such as xxx_1 and xxx_2 indic ates the relocated port number. the channel on such pin has multiple functions, each of which has its own pin name. use the e xtended p ort f unction r egister (epfr) to select the pin to be used .
document number: page 9 of 107 s6e1c3 series wns064 (top view) note: ? the number after the underscore ("_") in a pin name such as xxx_1 and xxx_2 indic ates the relocated port number. the channel on such pin has multiple functions, each of which has its own pin name. use the e xtended p ort f unction r egister (epfr) to select the pin to be used .
document number: page 10 of 107 s6e1c3 series lqa048 - 02 (top view) note: ? the number after the underscore ("_") in a pin name such as xxx_1 and xxx_2 indic ates the relocated port number. the channel on such pin has multiple functions, each of which has its own pin name. use the e xtended p ort f unction r egister (epfr) to select the pin to be used .
document number: page 11 of 107 s6e1c3 series wny048 (top view) note: ? the number after the underscore ("_") in a pin name such as xxx_1 and xxx_2 indic ates the relocated port number. the channel on such pin has multiple functions, each of which has its own pin name. use the e xtended p ort f unction r egister (epfr) to select th e pin to be used .
document number: page 12 of 107 s6e1c3 series lqb032 (top view) note: ? the number after the underscore ("_") in a pin name such as xxx_1 and xxx_2 indic ates the relocated port number. the channel on such pin has multiple functions, each of which has its own pin name. use the e xtended p ort f unction r egister (epfr) to select the pin to be used .
document number: page 13 of 107 s6e1c3 series wnu032 (top view) note: ? the number after the underscore ("_") in a pin name such as xxx_1 and xxx_2 indic ates the relocated port number. the channel on such pin has multiple functions, each of which has its own pin name. use the e xtended p ort f unction r egister (epfr) to select the pin to be used .
document number: page 14 of 107 s6e1c3 series wlcsp tbd note: ? the number after the underscore ("_") in a pin name such as xxx_1 and xxx_2 indic ates the relocated port number. the channel on such pin has multiple functions, each of which has its own pin name. use the e xtended p ort f unction r egister (epfr) to select the pin to be used .
document number: page 15 of 107 s6e1c3 series 4. list of pin functions list of pin numbers the numb er after the underscore ("_") in a pin name such as xxx_1 and xxx_2 indic ates the relocated port number. the channel on such pin has multiple functions, each of which has its own pin name. use the xtended unction egister (epfr) to select the pin to be used pin no. pin function i/o circuit type pin state type lqfp -64 qfn - 64 lqfp -48 qfn - 48 lqfp -32 qfn - 32 wlcsp (tbd) 1 1 p50 sin3_1 int00_0 p51 sot3_1 int01_0 4 p52 sck3_1 int02_0 4 4 p53 tioa1_2 int07_2 5 5 scs60_1 tiob0_1 int03_2 mi2sws6_1 p31 sck6_1 si2cscl6_1 int04_2 mi2sck6_1 5 p31 sck6_1 si2cscl6_1 int04_2 7 7 sot6_1 si2csda6_1 tiob2_1 int05_2 mi2sdo6_1 sot6_1 si2csda6_1 tiob2_1 int05_2
document number: page 1 of 107 s6e1c3 series pin no. pin function i/o circuit type pin state type lqfp - 64 qfn - 64 lqfp - 48 qfn - 48 lqfp - 32 qfn - 32 wlcsp (tbd) 8 8 adtg_6 sin6_1 int04_0 mi2sdi6_1 7 adtg_6 sin6_1 int04_0 9 p34 scs61_1 tiob4_1 mi2smck6_1 9 p34 scs61_1 mi2smck6_1 10 p35 scs62_1 tiob5_1 int08_1 11 tioa0_1 int03_0 rtcco_2 subout_2 ic1_cin_0 10 tioa0_1 int03_0 rtcco_2 subout_2 12 tioa1_1 ic1_data_0 11 tioa1_1 13 tioa2_1 ic1_rst_0 12 tioa2_1 14 tioa3_1 ic1_vpen_0
document number: page 17 of 107 s6e1c3 series pin no. pin function i/o circuit type pin state type lqfp - 64 qfn - 64 lqfp - 48 qfn - 48 lqfp - 32 qfn - 32 wlcsp (tbd) 15 tioa4_1 ic1_vcc_0 16 tioa5_1 ic1_clk_0 17 13 8 18 14 9 19 15 10 x1 p40 tioa0_0 int12_1 21 p41 tioa1_0 int13_1 p42 tioa2_0 p43 adtg_7 tioa3_0 24 p4c sck7_1 tiob3_0 16 p4c sck7_1 25 17 p4d sot7_1 18 p4e sin7_1 int06_2 27 19 11 vcc 28 12 29 21 13 vss 14 p46 31 15 p47 x1a 24 16 initx 25 17 tioa2_2 int15_1 cec1_0
document number: page 18 of 107 s6e1c3 series pin no. pin function i/o circuit type pin state type lqfp - 64 qfn - 64 lqfp - 48 qfn - 48 lqfp - 32 qfn - 32 wlcsp (tbd) 34 p1e rts4_1 mi2smck4_1 35 p1d cts4_1 mi2sws4_1 p1c sck4_1 mi2sck4_1 37 p1b sot4_1 mi2sdo4_1 p1b sot4_1 38 p1a sin4_1 int05_1 cec0_0 mi2sdi4_1 27 p1a sin4_1 int05_1 cec0_0 39 p1f adtg_5 40 28 18 p10 j an00 41 29 19 p11 j an01 sin1_1 int02_1 wkup1 42 p12 j an02 sot1_1 43 31 21 p13 j an03 sck1_1 rtcco_1 subout_1 44 p14 j an04 sin0_1 scs10_1 int03_1
document number: page 19 of 107 s6e1c3 series pin no. pin function i/o circuit type pin state type lqfp - 64 qfn - 64 lqfp - 48 qfn - 48 lqfp - 32 qfn - 32 wlcsp (tbd) 45 p15 j an05 sot0_1 scs11_1 46 34 j an06 sck0_0 tioa7_1 47 35 j an07 tiob7_1 48 24 vcc 49 37 avrh 50 38 25 avrl 51 39 p21 int06_1 wkup2 52 wkup4 53 40 27 p01 sot0_0 54 wkup5 55 41 28 sin0_0 tiob7_0 56 42 29 p05 md1 tioa5_2 int00_1 wkup3 57 43 vcc 58 44 p80 j udm0 59 45 31 p81 j udp0 46 vss 61 47 p61 uhconx0 tiob2_2 tiob6_1 wkup6
document number: page of 107 s6e1c3 series pin no. pin function i/o circuit type pin state type lqfp - 64 qfn - 64 lqfp - 48 qfn - 48 lqfp - 32 qfn - 32 wlcsp (tbd) 63 - - - p0c e k tioa6_1 wkup7 64 48 1 nmix wkup0 rtcco_0 subout_0 crout_1 *: in case of 32 pin package, avrh pin is internally connected to vcc pin.
document number: page 21 of 107 s6e1c3 series list of pin functions the number after the underscore ("_") in a pin name such as xxx_1 and xxx_2 indic ates the relocated port number. the channel on such pin has multiple functions, each of which has its own pin name. use the xtended unction egister (epfr) to select th e pin to be used pin function pin name function description pin no. lqfp -64 qfn - 64 lqfp -48 qfn - 48 lqfp -32 qfn - 32 wlcsp (tbd) adc adtg_5 a/d converter external trigger input pin 39 adtg_6 8 8 7 adtg_7 an00 a/d converter analog input pin. anxx describes adc ch.xx. 40 28 18 an01 41 29 19 an02 42 an03 43 31 21 an04 44 an05 45 an06 46 34 an07 47 35 base timer 0 tioa0_0 base timer ch.0 tioa pin tioa0_1 11 10 tiob0_1 base timer ch.0 tiob pin 5 5 base timer 1 tioa1_0 base timer ch.1 tioa pin 21 tioa1_1 12 11 tioa1_2 4 4 base timer 2 tioa2_0 base timer ch.2 tioa pin tioa2_1 13 12 tioa2_2 25 17 tiob2_1 base timer ch.2 tiob pin 7 7 tiob2_2 61 47 base timer 3 tioa3_0 base timer ch.3 tioa pin tioa3_1 14 tiob3_0 base timer ch.3 tiob pin 24 base timer 4 tioa4_1 base timer ch.4 tioa pin 15 tiob4_1 base timer ch.4 tiob pin 9 base timer 5 tioa5_1 base timer ch.5 tioa pin 16 tioa5_2 56 42 29 tiob5_1 base timer ch.5 tiob pin 10 base timer 6 tioa6_1 base timer ch.6 tioa pin tiob6_1 base timer ch.6 tiob pin base timer 7 tioa7_1 base timer ch.7 tioa pin 46 34 tiob7_0 base timer ch.7 tiob pin 55 41 28 tiob7_1 47 35 debugger serial wire debug interface clock input pin 53 40 27 serial wire debug interface data input / output pin 55 41 28
document number: page of 107 s6e1c3 series pin function pin name function description pin no. lqfp - 64 qfn - 64 lqfp - 48 qfn - 48 lqfp - 32 qfn - 32 wlcsp (tbd) external interrupt int00_0 external interrupt request 00 input pin 1 1 int00_1 56 42 29 int01_0 external interrupt request 01 input pin int02_0 external interrupt request 02 input pin 4 int02_1 41 29 19 int03_0 external interrupt request 03 input pin 11 10 int03_1 44 int03_2 5 5 int04_0 external interrupt request 04 input pin 8 8 7 int04_2 5 int05_1 external interrupt request 05 input pin 38 27 int05_2 7 7 int06_1 external interrupt request 06 input pin 51 39 int06_2 18 int07_2 external interrupt request 07 input pin 4 4 int08_1 external interrupt request 08 input pin 10 int12_1 external interrupt request 12 input pin int13_1 external interrupt request 13 input pin 21 int15_1 external interrupt request 15 input pin 25 17 nmix non maskable interrupt input pin 64 48 1 general purpose i/o port 0 52 p01 53 40 27 54 55 41 28 p05 56 42 29 64 48 1 p10 general purpose i/o port 1 40 28 18 p11 41 29 19 p12 42 p13 43 31 21 p14 44 p15 45 p1a 38 27 p1b 37 p1c p1d 35 p1e 34 p1f 39 p21 general purpose i/o port 2 51 39 47 35 46 34
document number: page of 107 s6e1c3 series pin function pin name function description pin no. lqfp - 64 qfn - 64 lqfp - 48 qfn - 48 lqfp - 32 qfn - 32 wlcsp (tbd) gpio p30 general purpose i/o port 3 5 5 p31 5 7 7 8 8 7 p34 9 9 p35 10 11 10 12 11 13 12 14 15 16 p40 general purpose i/o port 4 p41 21 p42 p43 p46 14 p47 31 15 p4c 24 16 p4d 25 17 p4e 18 p50 general purpose i/o port 5 1 1 p51 p52 4 p53 4 4 general purpose i/o port 6 25 17 p61 61 47 p80 general purpose i/o port 8 58 44 p81 59 45 31 general purpose i/o port e 18 14 9 19 15 10 multi function serial 0 sin0_0 multi function serial interface ch.0 input pin 55 41 28 sin0_1 44 sot0_0 (sda0_0) multi function serial interface ch.0 output pin. this pin operates as sot0 when used as a uart/csio/lin pin (operation mode 0 to 3) and as sda0 when used as an i2c pin (operation mode 4). 53 40 27 sot0_1 (sda0_1) 45 sck0_0 (scl0_0) multi function serial interface ch.0 clock i/o pin. this pin operates as sck0 when used as a csio pin (operation mode 2) and as scl0 when used as an i2c pin (operation mode 4). 46 34
document number: page 24 of 107 s6e1c3 series pin function pin name function description pin no. lqfp - 64 qfn - 64 lqfp - 48 qfn - 48 lqfp - 32 qfn - 32 wlcsp (tbd) multi function serial 1 sin1_1 multi function serial interface ch.1 input pin 41 29 19 sot1_1 (sda1_1) multi function serial interface ch.1 output pin. this pin operates as sot1 when used as a uart/csio/lin pin (operation mode 0 to 3) and as sda1 when used as an i2c pin (operation mode 4). 42 sck1_1 (scl1_1) multi function serial interface ch.1 clock i/o pin. this pin operates as sck1 when used as a csio pin (operation mode 2) and as scl1 when used as an i2c pin (operation mode 4). 43 31 21 scs10_1 multi function serial interface ch.1 serial chip select 0 input/output pin. 44 scs11_1 multi function serial interface ch.1 serial chip select 1 output pin. 45 multi function serial 3 sin3_1 multi function serial interface ch.3 input pin 1 1 sot3_1 (sda3_1) multi function serial interface ch.3 output pin. this pin operates as sot3 when used as a uart/csio/lin pin (operation mode 0 to 3) and as sda3 when used as an i2c pin (operation mode 4). sck3_1 (scl3_1) multi function serial interface ch.3 clock i/o pin. this pin operates as sck3 when used as a csio (operation mode 2) and as scl3 when used as an i2c pin (operation mode 4). 4 multi function serial 4 sin4_1 multi function serial interface ch.4 input pin 38 27 sot4_1 (sda4_1) multi function serial interface ch.4 output pin. this pin operates as sot4 when used as a uart/csio/lin pin (operation mode 0 to 3) and as sda4 when used as an i2c pin (operation mode 4). 37 sck4_1 (scl4_1) multi function serial interface ch.4 clock i/o pin. this pin operates as sck4 when used as a csio (operation mode 2) and as scl4 when used as an i2c pin (operation mode 4). cts4_1 multi function serial interface ch4 cts input pin 35 rts4_1 multi function serial interface ch4 rts output pin 34
document number: page 25 of 107 s6e1c3 series pin function pin name function description pin no. lqfp - 64 qfn - 64 lqfp - 48 qfn - 48 lqfp - 32 qfn - 32 wlcsp (tbd) multi function serial 6 sin6_1 multi function serial interface ch.6 input pin 8 8 7 sot6_1 (sda6_1) multi function serial interface ch.6 output pin. this pin operates as sot6 when used as a uart/csio/lin pin (operation mode 0 to 3) and as sda6 when used as an i2c pin (operation mode 4). 7 7 sck6_1 (scl6_1) multi function serial interface ch.6 clock i/o pin. this pin operates as sck6 when used as a csio (operation mode 2) and as scl6 when used as an i2c pin (operation mode 4). 5 scs60_1 multi function serial interface ch.6 serial chip select 0 input/output pin. 5 5 scs61_1 multi function serial interface ch.6 serial chip select 1 output pin. 9 9 scs62_1 multi function serial interface ch.6 serial chip select 2 output pin. 10 multi function serial 7 sin7_1 multi function serial interface ch.7 input pin 18 sot7_1 (sda7_1) multi function serial interface ch.7 output pin. this pin operates as sot7 when used as a uart/csio/lin pin (operation mode 0 to 3) and as sda7 when used as an i2c pin (operation mode 4). 25 17 sck7_1 (scl7_1) multi function serial interface ch.7 clock i/o pin. this pin operates as sck7 when used as a csio (operation mode 2) and as scl7 when used as an i2c pin (operation mode 4). 24 16
document number: page of 107 s6e1c3 series pin function pin name function description pin no. lqfp - 64 qfn - 64 lqfp - 48 qfn - 48 lqfp - 32 qfn - 32 wlcsp (tbd) i2s(mfs) mi2sdi4_1 i2s serial data input pin (operation mode 2). 38 mi2sdo4_1 i2s serial data output pin (operation mode 2). 37 mi2sck4_1 i2s serial clock output pin (operation mode 2). mi2sws4_1 i2s word select output pin (operation mode 2). 35 mi2smck4_1 i2s master clock input /output pin (operation mode 2). 34 mi2sdi6_1 i2s serial data input pin (operation mode 2). 8 8 mi2sdo6_1 i2s serial data output pin (operation mode 2). 7 7 mi2sck6_1 i2s serial clock output pin (operation mode 2). mi2sws6_1 i2s word select output pin (operation mode 2). 5 5 mi2smck6_1 i2s master clock input /output pin (operation mode 2). 9 9 smart card interface ic1_cin_0 smart card insert detection output pin 11 ic1_clk_0 smart card serial interface clock output pin 16 ic1_data_0 smart card serial interface data input pin 12 ic1_rst_0 smart card reset output pin 13 ic1_vcc_0 smart card power enable output pin 15 ic1_vpen_0 smart card programming output pin 14 usb udm0 usb function/host d pin 58 44 udp0 usb function/host d + pin 59 45 31 uhconx0 usb external pull up control pin 61 47 real time clock rtcco_0 0.5 seconds pulse output pin of real time clock 64 48 1 rtcco_1 43 31 21 rtcco_2 11 10 subout_0 sub clock output pin 64 48 1 subout_1 43 31 21 subout_2 11 10 cec/re mote control reception cec0_0 cec/remote control reception ch.0 input/output pin 38 27 cec1_0 cec/remote control reception ch.1 input/output pin 25 17
document number: page 27 of 107 s6e1c3 series pin function pin name function description pin no. lqfp - 64 qfn - 64 lqfp - 48 qfn - 48 lqfp - 32 qfn - 32 wlcsp (tbd) low power consumption mode wkup0 deep standby mode return signal input pin 0 64 48 1 wkup1 deep standby mode return signal input pin 1 41 29 19 wkup2 deep standby mode return signal input pin 2 51 39 wkup3 deep standby mode return signal input pin 3 56 42 29 wkup4 deep standby mode return signal input pin 4 52 wkup5 deep standby mode return signal input pin 5 54 wkup6 deep standby mode return signal input pin 6 wkup7 deep standby mode return signal input pin 7 i2c slave si2cscl6_1 i2c clock pin 5 si2csda6_1 i2c data pin 7 7 initx external reset input pin. a reset is valid when initx="l". 24 16 mode 0 pin. during normal operation, input md0="l". during serial programming to flash memory, input md0="h". 17 13 8 md1 mode 1 pin. during normal operation, input is not needed. during serial programming to flash memory, md1 = "l" must be input. 56 42 29 main clock (oscillation) input pin 18 14 9 sub clock (oscillation) input pin 14 x1 main clock (oscillation) i/o pin 19 15 10 x1a sub clock (oscillation) i/o pin 31 15 crout_1 built in high speed cr oscillation clock output port 64 48 1 vcc power supply pin 27 19 11 vcc 48 24 vcc 57 43 gnd vss gnd pin 29 21 13 vss 46 analog reference avrh a/d converter analog reference voltage input pin 49 37 avrl a/d converter analog reference voltage input pin 50 38 25 c pin power supply stabilization capacitance pin 28 12 *: in case of 32 - pin package, avrh pin is internally connected to vcc pin.
document number: page 28 of 107 s6e1c3 series 5. i /o circuit type type circuit remarks a p-ch ch nch digital output digital output digital input standby mode control clock input standby mode control ch ch nch digital output digital output digital input standby mode control pullup resistor control 1 pullup resistor control ? oscillation feedback resistor : approximately 1m ? with standby mode control when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 33k ? i oh = - 4ma, i ol = 4ma b digital input pullup resistor k
document number: page 29 of 107 s6e1c3 series type circuit remarks c p-ch ch nch ch ch nch 1 digital output digital output digital input standby mode control clock input standby mode control digital output digital output digital input standby mode control pullup resistor control pullup resistor control ? oscillation feedback resistor : approximately 5m ? with standby mode control when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 33k i oh = - 4ma, i ol = 4ma
document number: page of 107 s6e1c3 series type circuit remarks d p-ch ch nch digital output digital output digital input standby mode control pullup resistor control ? mos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 33k ? ioh= - 4 ma, iol= 4 ma ? when this pin is used as an i2c pin, the digital output p - ch transistor is always off e p-ch ch nch digital output digital output digital input standby mode control pullup resistor control wake up request wake up control ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 33k ? ioh= - 4ma, iol= 4ma ? when this pin is used as an i2c pin, the digital output p - ch transistor is always off
document number: page 31 of 107 s6e1c3 series type circuit remarks f p-ch ch nch analog input input control digital output digital output digital input standby mode control pullup resistor control ? cmos level output ? cmos level hysteresis input ? with input control ? analog input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 33k ? ioh= - 4ma, iol= 4ma ? when this pin is used as an i2c pin, the digital output p - ch transistor is always off g p - ch ch n ch analog input input control digital output digital output digital input standby mode control pull up resistor control wake up request wake up control ? cmos level output ? cmos level hysteresis input ? with input control ? analog input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 33k ? ioh= - 4ma, iol= 4ma ? when this pin is used as an i2c pin, the digital output p - ch transistor is always off
document number: page of 107 s6e1c3 series type circuit remarks h p - ch ch n ch digital output digital output digital input standby mode control pull up resistor control ? cmos level output ? cmos level hysteresis input ? 5v tolerant ? with pull - up resistor control ? with standby mode control ? pull - up resistor : ap proximately 33k ? ioh= - 4ma, iol= 4ma ? available to control pzr registers ? when this pin is used as an i2c pin, the digital output p - ch transistor is always off i mode input ? cmos level hysteresis input j differential differential input udp input udm input usb / gpio select gpio digital input gpio digital input gpio digital input circuit control gpio digital input / output direction gpio digital input usb digital input / output direction udm output udp output usb full speed / speed control gpio digital input circuit control gpio digital input / output direction gpio digital output udp / 81 udm / 80 full - speed, low - speed control when the gpio is selected. x cmos level output x cmos level hysteresis input x with standby mode control
document number: page of 107 s6e1c3 series 6. handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the co nditions in which they are used (circuit conditions, environmental conditions, etc.). this page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your spansion semiconductor devices. 6.1 precautions for product design this section describes precautions when designing electronic equipment using semiconductor devices. absolut e maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. do not exceed these ratings. recommended operating c onditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operat ing conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering applica tion outside the listed conditions are advised to contact their sales representative beforehand. processing and protection of pins these precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/outpu functions. (1) preventing over voltage and over current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the dev and in extreme cases leads to permanent damage of the device. try to prevent such overvoltage or over current conditions at the design stage. (2) protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. such conditions if present for extended periods of time can damage the device. therefore, avoid this type of connection. (3) handling of unused input pins unconnected input pins with very high impedance levels ca n adversely affect stability of operation. such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
document number: page 34 of 107 s6e1c3 series latch - up semiconductor devices are constructed by the formation of p type and n type areas on a substrate. w hen subjected to abnormally high voltages, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. this condition is called la tch up. caution: the occurrence of latch up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: (1) be sure that voltages applied to pins do not exceed the absolute maximum ratings. this should include attention to abnormal noise, surge levels, etc. (2) be sure that abnormal current flows do not occur during the power on sequence. observance of safety regulations and standards most c ountries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. customers are requested to observe applicable regulations and standards in the design of products. fail - safe design any se miconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention o f over current levels and other abnormal operating conditions. precautions related to usage of devices spansion semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, commun ications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may direct ly affect human lives or cause physical injury or proper ty damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales represent atives before such use. the company will not be responsible for damages arising from such use without prior approval. 6.2 precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either case, for heat resist ance during soldering, you should only mount under spansion 's recommended conditions. for detailed information about mount conditions, contact your sales representative. lead insertion type mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. direct mounting onto boards normally involves processes for inserting leads into through holes on the board and using the flow soldering (wave soldering) metho d of applying liquid solder. in this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to spansion recommended mounting conditions if socket mounting is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic lead s be verified before mounting.
document number: page 35 of 107 s6e1c3 series surface mount type surface mount packaging has longer and thinner leads than lead insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch resu lts in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting techniques. spansion recommends the solder reflow method, and has established a ranking of mounting conditions for each product. users are advised to mount packages in accordance with spansion ranking of recommended conditions. lead - free packaging caution: when ball grid array (bga) packages with sn ag cu balls are mounted using sn pb eutectic soldering, junction strength may be reduced under some conditions of use. storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorpt ion of moisture. during mounting, the applic ation of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. to prevent, do the following: (1) avoid exposure to rapid temperature changes, which cause moisture to condense in side the product. store products in locations where temperature changes are slight. (2) use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5 ? and 30 ? hen you open dry package that rec ommends humidity 40% to 70% relative humidity. (3) when necessary, spansion packages semiconductor devices in highly moisture resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for storag (4) avoid storing packages where they are exposed to corrosive gases or high levels of dust. baking packages that have absorbed moisture may be de moisturized by baking (heat drying). follow the spansion recommended conditions for baking. condition: 125 c/24 h static electricity because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following preca utions: (1) maintain relative humidity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. (2) electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) eliminate static body electricity by the use of rings or bracelets connected to ground th rough high resistance (on the level of 1 ). wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) ground all fixtures and instruments, or protect with anti static measures. (5) avoid the use of styrofoam or other highly static prone materials for storage of completed board assemblies.
document number: page of 107 s6e1c3 series 6.3 precautions for use environment reliability of semiconductor devices depends on ambient temperature and other conditions as described above. for reliable performance, do the following: (1) humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti humidity processing. (2) discharge of static e lectricity when high voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. in such cases, use anti static measures or processing to prevent discharges. (3) corrosive gases, dust, or oil exposure to corrosive gases o r contact with dust or oil may lead to chemical reactions that will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) radiation, including cosmic radiation most devices are not designed for environments involving exposure to radiation or cosmic radiation. users should provide shielding as appropriate. (5) smoke, flame caution: plastic molded devices are flammable, and therefore should not be used near combustible substan ces. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of spansion products in other special environmental conditions should consult with sales representatives.
document number: page 37 of 107 s6e1c3 series 7. handling devices power supply pins in products with multiple v and v pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch up. however, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with eac h power supply pin and gnd pin of this device at low impedance. it is also advisable that a ceramic capacitor of approximately 0.1 f be connected as a bypass capacitor between each power supply pin and gnd pin , between avrh pin and avrl pin near this devi stabilizing supply voltage a malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommende d operating conditions of the vcc power supply voltage. as a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in vcc ripple ( peak peak value) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the vcc value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 v/s when there is a momentary fluctuation on switching the power supply. crystal oscillator circuit noise near the x0 /x1 and x0a/ x1 pins may cause the device to malfunction. design the printed circuit board so that x0 / x1, x0a/x1a pins, the cry stal oscillator, and the bypass capacitor to ground are located as close to the device as possible. it is strongly recommended that the pc board artwork be designed such that the x0 /x1 and x0a/ x1 pins are surrounded by ground plane as this is expected to produce stable operation. evaluate oscillation of your using crystal oscillator by your mount board. sub crystal oscillator this series sub oscillator circuit is low gain to keep the low current consumption. the crystal oscillator to fill the follow ing con ditions is recommended for sub crystal oscillator to stabilize the oscillation. ? surface mount type size: more than 3.2 mm 1.5 mm load capacitance: appro xima tely 6 pf 7 pf ? lead type load capacitance: approximately 6 pf 7 pf
document number: page 38 of 107 s6e1c3 series using an external clock when using an external cloc k as an input of the main clock set x0 / x1 to the external clock input, and input the clock to x0 x1 (pe3) can be used as a general purpose i/o port. similarly, hen using an external cloc k as an input of the sub clock set a/ x1 to the external clock input, and input the clock to x1 a (p47) can be used as a general purpose i/o port. however in the deep standby mode, an external clock a s an input of the sub clock can not be used. handling when using multi - function serial pin as i 2 c pin if it is using the multi function serial pin as i c pins, p ch transistor of digital output is always disable d c pins need to keep the electrical characteristic like other pins and not to connect to the external i c bus system with power off. c pin this series contains the regulator. be sure to connect a smoothing capac itor (c ) for the regulator between the c pin and the gnd pin. please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. however, some laminated ceramic capacitors have the characteristics of capacitan ce variation due to thermal fluctuation (f characteristics and y5v characteristics). please select the capacitor that meets the specifications in the operating conditio ns to use by evaluating the temperature characteristics of a capacitor. a smoothing capa citor of about 4.7 f would be recommended for this series. incidentally, the c pin becomes floating in deep standby mode. mode pins (md0) connect the md pin (md0) directly to v or v pins. design the printed circuit board such that the pull up/down resistance stays low, as well as the distance between the mode pins and v pins or v pins is as short as possible and the connection impedance is low, when the pins are pulled up/down such as for switching the pin level and rewriting the flash memory data. it is because of preventing the device erroneously switching to test mode due to noise. example of using an external clock device 0 ( ) x1 (pe3), x1a (p47) can be used as general purpose i/o ports. vss gnd set as external clock input
document number: page 39 of 107 s6e1c3 series notes on power - on turn power on/off in the following order or at the same time. turning on : vcc avrh turning off : avrh vcc serial communication there is a possibility to receive wrong data due to the noise or other causes on the serial communication. therefore, design a printed circuit board so as to avoid noise. consider the case of receiving wrong data due to noise perfor m error detection such as by applying a checksum of data at the end. if an error is detected retransmit the data. differences in features among the products with different memory sizes and between flash memory products and mask products the electric chara cteristics including power consumption, esd, latch up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between flash memory products and mask products are different because chip layout and memory st ructures are different. if you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics pull - up function of 5 v tolerant i/o please do not input the signal more than vcc voltage at the time of pull up function use of 5 v tolerant i / handling when using debug pins when debug pins ( swdio/swclk ) are set to gpio or other peripheral functions, set them as output only; do not set them as input.
document number: page 40 of 107 s6e1c3 series 8. block diagram sw-dp nvic fast flash i/ security bit band wrapper system rom table dualtimer watchdog timer (software) clock reset generator watchdog timer (hardware) watchdog timer (cvs) 64ch bridge phy main osc sub osc 8 100 source clock unit 12- bit a/ d converter lvd ctrl watch counter realtime clock speed cr peripheral clock gating pinfunction lvd regulator swclk swdio base timer 168 ch 4 ch external interrupt 12 pin(max) + nmi smart card i/ initx x0 x1 x0a x1a crout avrh anxx adtg tioax tiobx udp0, udm0 uhconx0 c rtcco intx nmix md0, md1 p0x, p1x, : pex sckx sinx sotx scsx mi2sckx mi2sdix mi2sdox mi2smckx mi2 swsx ic1_clkx ic1_vccx ic1_vpenx ic1_cinx ic1_datax on-chip sram 12/16kbyte chip flash 64/128 kbyte multifunction serial / ch. (max) avrl i2c slave si2 csdax si2 csclx cortex-m0core ahb - apb bridge multilayer ahb apb bridge : 1 usb (host/) crc accelarator deep standby ctrl wkupx
document number: page 41 of 107 s6e1c3 series 9. memory map memory map (1) see "memory map (2)" for the memory size details.
document number: page 42 of 107 s6e1c3 series memory map (2) *: see " s6e1c1/c3 series flash programming manual" to check details of the flash memory. s6e1c31b0a s6e1c31c0a s6e1c31d0a s6e1c32b0a s6e1c32c0a s6e1c32d0a 0x2008_0000 0x2008_0000 0x2000_4000 0x2000_4000 0x2000_3000 0x2000_3000 0x2000_1000 0x2000_0000 0x0010_0004 cr trimming 0x0010_0004 cr trimming 0x0010_0000 security 0x0010_0000 security 0x0001_fff0 0x0000_fff0 0x0000_0000 0x0000_0000 reserved reserved 4k byte 12k byte 4k byte 8k byte reserved reserved reserved reserved flash 65520 byte (64kbyte - 16byte) * flash 131056 byte (128kbyte - 16byte)
document number: page 43 of 107 s6e1c3 series peripheral address map start addre ss end address bus peripheral 0x4000_0000 0x4000_0fff flash memory i/f register 0x4000_1000 0x4000_ffff reserved 0x4001_0000 0x4001_0fff clock/reset control 0x4001_1000 0x4001_1fff hardware watchdog imer 0x4001_2000 0x4001_2fff software watchdog imer 0x4001_3000 0x4001_4fff reserved 0x4001_5000 0x4001_5fff dual timer 0x4001_6000 0x4001_ffff reserved 0x4002_0000 0x4002_0fff apb1 reserved 0x4002_1000 0x4002_3fff reserved 0x4002_4000 0x4002_4fff reserved 0x4002_5000 0x4002_5fff base timer 0x4002_6000 0x4002_6fff reserved 0x4002_7000 0x4002_7fff a/d converter 0x4002_8000 0x4002_dfff reserved 0x4002_e000 0x4002_efff built cr trimming 0x4002_f000 0x4002_ffff reserved 0x4003_0000 0x4003_0fff external interrupt controller 0x4003_1000 0x4003_1fff interrupt request batch read function 0x4003_2000 0x4003_2fff reserved 0x4003_3000 0x4003_3fff 0x4003_4000 0x4003_4fff /remote control receiver 0x4003_5000 0x4003_5 voltage / ds mode / vref calibration 0x4003_6 0x4003_6f usb clock generator 0x4003_ 70 0x4003_7 7 reserved 0x4003_7800 0x4003_79ff i2c slave 0x4003_7a00 0x4003_7fff reserved 0x4003_8000 0x4003_8fff multi function erial interface 0x4003_9000 0x4003_9fff 0x4003_a000 0x4003_afff watch counter 0x4003_b000 0x4003_bfff eal time clock 0x4003_c000 0x4003_c speed cr prescaler 0x4003_c100 0x4003_c7ff peripheral clock gating 0x4003_ c8 0x4003_ c8 reserved 0x4003_c900 0x4003_c9ff smart card nterface 0x4003_ca00 0x4003_caff i2s clock generator 0x4003_ 0x4003_ reserved 0x4004_0000 0x400 4 _ffff usb ch.0 0x400 5 _0000 0x4006_0fff reserved 0x4006_1000 0x4006_1fff 0x4006_ 0x41ff_ffff reserved
document number: page 44 of 107 s6e1c3 series 10. pin status in each cpu state the following table shows pin status in each cpu stat (1) (2) (3) (4) (5) (6) (7) (8) main osillation circuit selected *1 main osillation circuit selected os os oe oe oe os os os main clock external input selected - - ie/is ie/is ie/is is is is gpio selected - - pc hc is hs is hs main osillation circuit selected *1 main osillation circuit selected os os oe oe oe os os os digital i/o slected *2 gpio selected - - pc hc is gs is gs sub osillation circuit selected *1 sub osillation circuit selected os oe oe oe oe oe oe oe sub clock external input selected - - ie/is ie/is ie/is is is is gpio selected - - pc hc is hs is hs sub osillation circuit selected *1 sub osillation circuit selected os oe oe oe oe oe oe oe digital i/o slected *2 gpio selected - - pc hc is hs is hs e digital i/o slected initx input f digital i/o slected md0 input usb i/o selected *7 usb port selected - - ue us us us us us digital i/o slected *6 gpio selected is ie cp hc is hs is hs sw selected is ip *5 pc ip ip ip ip ip gpio selected - - pc hc is hs is hs nmi selected - - ip ip ip - - - wkup0 enable and input selected - - ip ip ip ip ip ip gpio selected is ie pc hc is - - - analog input selected *3 analog input selected wkup enable and input selected - - ip ip ip ip ip ip exterrnal interrupt enable and input selected - - ip ip ip gs is gs gpio selected - - pc hc is hs is hs resource other than above selected - - pc hc is gs is gs cec pin selected - - cp cp cp cp cp cp wkup enable and input selected - - ip ip ip ip ip ip i2cslave enable selected - - pc hc ip gs is gs exterrnal interrupt enable and input selected - - pc hc ip gs is gs gpio selected is ie pc hc is hs is hs resource other than above selected - - pc hc is gs is gs this pin is digital input pin, pull up register is on, and digital input is not shut off in all cpu state.. this pin is digital input pin, pull up register is none, digital input is not shut off in all cpu state.. digital i/o slected *4 digital i/o slected analog input is enalbe in all cpu state digital i/o slected digital i/o slected type selected pin function cpu state digital i/o slected *2 digital i/o slected *2 k a b c j d g h i
document number: page 45 of 107 s6e1c3 series each term above table have the following meaning s type this indicates a pin status type that is show pin list table 4 list of functions selected pin function this indicates a pin function that is selected by user program. cpu s t ate this indicates a state of the cpu that is shown below. (1) reset s ate. cpu is initialized by on reset or a reset due to low power voltage supply. (2) reset s ate. cpu is initialized by initx input signal or system initialization after power on reset. (3) run mode or sleep mode state (4) timer mode rtc mode stop mode state he standby pin level setting bit (spl) in the standby mode control register (stb_ctl) is set to "0". (5) timer mode rtc mode stop mode state he standby pin level setting bit (spl) in the standby mode control register (stb_ctl) is set to " 1 ". (6) deep standby s mode or deep standby rtc mode state he standby pin level setting bit (spl) in the standby mode control register (stb_ctl) is set to " " (7) deep standby s mode or deep standby rtc mode state he standby pin level setting bit (spl) in the standby mode control register (stb_ctl) is set to " 1 " (8) run mode state after returning from deep standby mode. (i/o state hold function(contx) is fixed at 1)
document number: page 46 of 107 s6e1c3 series each pin status the meaning of the s ymbols in the pin status table is as follows. digital output is disabled (hi ) pull up register is off. digital input is shut off by fixed 0. digital output is disabled ( ) pull up register is off. digital input is not shut off. digital output is disabled ( ) pull up register is defined by the value of the pcr register. digital input is not shut off. ie/is digital output is disabled ( ) pull up register is off. digital input is shut off in case of the stop. digital input is not shut off in case of the operation. the is operation state. however, it may be stopped in some operation mode of the cpu. for detail, see chapter low power consumption mode in peripheral manual the osc s stop state. ( ) ue usb i/o function is controlled by usb controller. us usb i/o function is disable d ( ) digital output and pull up register is controlled by the register in the gpio or peripheral function. digital input is not shut off digital output is controlled by the register in the gpio or peripheral function. pull up register is off digital input is not shut off digital output and pull up register is maintained the status that is immediately prior to entering the current cpu state. digital input is not shut off digital output and pull up register is maintained the status that is immediately prior to entering the current cpu state. digital input is shut off digital output and pull up register is copied the gpio status that is immediately prior to entering the current cpu state and the s atus is maintained. digital input is shut off additional note additional note is described below. *1 in this type, when internal oscillation fu is selected, digital output is disabled ( ) pull up register is off , d igital input is shut off by fixed 0. in this type, when digital i/o function is selected, internal oscillation function is d isabled. in this type, when analog input function is sele ted, digital output is disabled ( ). pull up register is off digital input is shut off by fixed 0. *4 in this type, when digital i/o function is selected, an a log input function is not available. *5 in this case, pcr register is initialized to 1 . pull up register is on. in this type, when digital i/o function is selected, usb i/o function is disab d. this pin does not have pull up register. 7 in this type, when usb i/o function is sele ted, digital output is disable d (hi z) digital input is shut off by fixed 0.
document number: page 47 of 107 s6e1c3 series 11. electrical characteristics 11.1 absolute maximum ratings parameter symbol rating unit remarks min max power supply voltage* 1, v v 0.5 v 4.6 v analog reference voltage* 1, avrh v 0.5 v 4.6 v input voltage* 1 v v 0.5 v + 0.5 ( 4.6 v) v v 0.5 v + 6.5 v 5 v tolerant analog pin input voltage* 1 v v 0.5 v + 0.5 ( 4.6 v) v output voltage* 1 v v 0.5 vcc + 0.5 ( 4.6 v) v l level maximum output current* 4 10 ma 4 ma type l level average output current* 5 olav 4 ma 4 ma type l level total maximum output current 100 ma l level total average output current* olav 50 ma h level maximum output current* 4 10 ma 4 ma type h level average output current* 5 ohav 4 ma 4 ma type h level total maximum output current 100 ma h level total average output current* ohav 50 ma power consumption mw storage temperature 55 + 150 *1: these parameters are based on the condition that v = v. *2: v must not drop below v 0.5 v. : ensure that the voltage does not to exceed v 5 v at power 4 : the maximum output current is the peak value for a single pin. 5 : the average output is the average current for a single pin over a period of 100 ms. : the total average output current is the average current fo r all pins over a period of 100 ms. < warning > ? semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings.
document number: page 48 of 107 s6e1c3 series 11.2 recommended operating conditions (v = v) parameter symbol conditions value unit remarks min max power supply voltage v 1.65 * v v *1 analog reference voltage avrh 2.7 v v v 2.7 v v v v v < 2.7 v avrl vss vss v smoothing capacitor 1 10 f for regulator* operating emperature ta 40 10 5 1 : when p81 / udp0 and p80 /udm0 pins are used as usb (udp0, udm0). : see "c pin" in " 7 handling devices " for the connection of the smoothing capacitor. : in between less than the minimu m power supply voltage reset / interrupt detection voltage or more, instruction execution and low voltage detection function by built in high speed cr (including main pll is used) or built speed cr is possible to operate only. < warning > 1. the recomm ended operating conditions are reuired in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. 2. alwas use semiconductor devices with in their recommended operating condition ranges. operation outside these ranges ma adversel affect reliabilit and could result in device failure. 3. no warrant is made with respect to uses operating conditions or combinations not represented on the data sheet. 4. users considering application outside the listed conditions are advised to contact their representatives beforehand.
document number: page 49 of 107 s6e1c3 series 11.3 dc characteristics 11.3.1 current rating symbol (pin name ) conditions hclk frequency *4 value unit remarks typ *1 max *2 icc (vcc) run mode, code executed from flash 8 mhz external clock input, pll on *8 nop code executed built in high speed cr stopped all peripheral clock stopped by ckenx 8 1.4 2.7 ma 2.6 4.1 40 3.9 5.6 8 mhz external clock input, pll on *8 benchmark code executed built in high speed cr stopped pclk1 stopped 8 1.3 2.6 ma 2.3 3.8 40 3.4 5.1 8 mhz crystal oscillation, pll on *8 nop code executed built in high speed cr stopped all peripheral clock stopped by ckenx 8 1.6 3.0 ma , *9 2.8 4.4 40 4.1 5.9 run mode, code executed from ram 8 mhz external clock input, pll on *8 nop code executed built in high speed cr stopped all peripheral clock stopped by ckenx 8 1.0 2.1 ma 1.7 2.9 40 2.7 4.0 run mode, code executed from flash 8 mhz external clock input, pll on nop code executed built in high speed cr stopped pclk1 stopped 40 1.6 3.1 ma ,*6,*7 run mode, code executed from flash built in high speed cr *5 nop code executed all peripheral clock stopped by ckenx 8 1. 1 2.4 ma khz crystal oscillation nop code executed all peripheral clock stopped by ckenx k 240 1264 a built in low speed cr nop code executed all peripheral clock stopped by ckenx 100 k 246 1271 a iccs (vcc) sleep operation 8 mhz external clock input, pll on *8 all peripheral clock stopped by ckenx 8 0.8 1.9 ma 1.3 2.4 40 1.8 3.0 built in high speed cr *5 all peripheral clock stopped by ckenx 8 0.6 1.7 ma khz crystal oscillation all peripheral clock stopped by ckenx k 237 1261 a built in low speed cr all peripheral clock stopped by ckenx 100 k 238 1262 a *1 : =+25 v =3. v *2 : =+ 105 v =3.6 v *3 : all ports are fixed *4 : pclk0 is set to divided rate 8 *5 : the frequency is set to 8 mhz by trimming *6 : flash sync down is set to frwtr.rwt= 1 11 and fsyndn.sd=1111 *7 : vcc= 1 65 v *8 : when hclk= 8 9 : when imainsel bit( _ctl: imainsel ) is 1 (default)
document number: page 50 of 107 s6e1c3 series parameter symbol (pin name ) conditions value unit remarks typ max power supply current (vcc) stop mode ta=25 vcc= v 1 .4 52.4 *1 ta=25 vcc= 1.65 v 1 52.0 *1 ta = 105 vcc= v 597 *1 (vcc) sub timer mode ta=25 vcc= v khz crystal oscillation 1 5.6 55.6 *1 ta=25 vcc= 1.65 v khz crystal oscillation 1 5.0 55.0 *1 ta = 105 vcc= v khz crystal oscillation 601 *1 (vcc) rtc mode ta=25 vcc= v khz crystal oscillation 1 53.2 *1 ta=25 vcc= 1.65 v khz crystal oscillation 1 2.7 52.7 *1 ta = 105 vcc= v khz crystal oscillation 598 *1 *1: l ports are fixed. lvd off. flash off. : when caldone bit( cal_ctl:caldone) is 1 n case of , bipolar vref current is added.
document number: page 51 of 107 s6e1c3 series parameter symbol (pin name ) conditions value unit remarks typ max power supply current (vcc) deep standby stop mode ram off ta=25 vcc= v 0.58 1.85 *1 ta=25 vcc= 1.65 v 0.56 1.83 *1 ta = 105 vcc= v 46 *1 ta=25 vcc= v 0.78 *1 ta=25 vcc= 1.65 v 0.76 *1 ta = 105 vcc= v 88 *1 (vcc) deep standby rtc mode ram off ta=25 vcc= v 1.16 2.4 *1 ta=25 vcc= 1.65 v 1.15 2.4 *1 ta = 105 vcc= v 46 *1 ta=25 vcc= v 1.37 7.2 *1 ta=25 vcc= 1.65 v 1.35 7.2 *1 ta = 105 vcc= v 88 *1 *1: l ports are fixed. lvd off. : when caldone bit(cal_ctl:caldone) is 1 n case of , bipolar vref current is added.
document number: page 52 of 107 s6e1c3 series lvd current (v = 1.65 v to 3.6 v, v = v, = 40c to 105 c) parameter symbol pin name conditions value unit remarks typ max low - v oltage detection circuit (lvd) power supply current cclvd vcc at operation 0.15 occurrence of reset 0.10 occurrence of interrupt bipolar vref current (v =1.65 v to 3.6 v, v = v, = 40c to 105 c) parameter symbol pin name conditions value unit remarks typ max bipolar vref current vcc at operation 100 flash memory current (v = 1.65 v to 3.6 v, v = v, = 40c to 105 c) parameter symbol pin name conditions value unit remarks typ max flash m emory rite/ rase current vcc at write/erase 4.4 5.6 ma a/d converter current (v = 1.65 v to 3.6 v, v = v, = 40c to 105 c) parameter symbol pin name conditions value unit remarks typ max power supply current vcc at operation 0.5 0.75 ma reference power supply current (avrh ) ccavrh avrh at operation 0.69 1.3 ma avrh=3.6 v at stop 0.1 1.3
document number: page 53 of 107 s6e1c3 series peripheral current dissipation (v = 1.65 v to 3.6 v, v = v, = 40c to 10 5 c) clock system peripheral conditions frequency (mhz) unit remarks 8 20 40 hclk gpio at a ll ports operation 0.05 0.12 0.23 ma at 2ch operation 0.02 0.06 0.10 usb at 1ch operation 0.13 0.13 0.13 ma *1 pclk1 base timer 4ch operation 0.02 0.05 0.10 ma 1 unit operation 0.04 0.10 0.21 multi function serial 1ch operation 0.01 0.03 0.06 mfs - i2s at 1ch operation 0.02 0.05 0.08 smart card i/f 1ch operation 0.04 0.08 0.18 *1 usb itself uses 48mhz clock
document number: page 54 of 107 s6e1c3 series 11.3.2 pin characteristics (v = 1.65 v to 3.6 v, v = v, = 40 10 5 ) parameter symbol pin name conditions value unit remarks min typ max h level input voltage (hysteresis input) v hysteresis input pin, v 2.7 v v 0.8 v v v 2.7 v v 7 5 v tolerant input pin v 2.7 v v 0.8 v 5.5 v v 2.7 v v 7 level input voltage (hysteresis input) v hysteresis input pin, v 2.7 v v v v v 2.7 v v 5 v tolerant input pin v 2.7 v v v v v 2.7 v v output voltage v 4 ma type v 2.7 v = 4 ma v 0.5 v v v 2.7 v = ma v 4 5 output voltage v 4 ma type v 2.7 v 4 ma v 0.4 v v 2.7 v = ma input leak current 5 + 5 pull up resistance value pu pull up pin v 2.7 v 21 48 k v 2.7 v 88 input capacitance in other than vcc, vss, avrh 5 15 pf
document number: page 55 of 107 s6e1c3 series 11.4 ac characteristics 11.4.1 main clock input characteristics (v = 1.65 v to 3.6 v, v = v, = 40c to 10 5 c) parameter symbol pin name conditions value unit remarks min max input frequency x1 v 2.7 v 8 4 8 when the crystal oscillator is connected v 2.7 v 8 8 4 8 when the external lock is used input clock cycle cylh 20.83 125 ns when the external lock is used input clock pulse width /t cylh /t cylh 45 55 % when the external lock is used input clock ris ing time and fall ing time 5 ns when the external lock is used internal operating lock *1 frequency 40 .8 master clock 40 .8 base clock (hclk/fclk) 40 .8 apb0 bus clock* cp1 40 .8 apb1 bus clock* internal operating clock *1 cycle time cyccm 24.5 ns master clock cycc 24.5 ns base clock (hclk/fclk) cycp0 24.5 ns apb0 bus clock* cycp1 24.5 ns apb1 bus clock* *1: details of each internal operating clock , refer to " chapter : clock " in " family peripheral manual ". *2: details of the apb bus to which a peripheral is connected , see " 8 block diagram ". 0.8 vcc cylh 0.8 vcc 0.2 vcc 0.2 vcc 0.8 vcc
document number: page 56 of 107 s6e1c3 series 11.4.2 sub clock input characteristics (v = 1.65 v to 3.6 v, v = 0 v, = 40 10 5 ) parameter symbol pin name conditions value unit remarks min typ max input frequency f x1a 32.768 khz when the crystal oscillator is connected 100 khz when the external lock is used input clock cycle cyll 10 31.25 s when the external lock is used input clock pulse width /t cyll /t cyll 45 55 % when the external lock is used *: see " ub crystal oscillator " in " 7 handling devices " for the crystal oscillator used. 0.8 vcc cyll 0.8 vcc 0.2 vcc 0.2 vcc 0.8 vcc
document number: page 57 of 107 s6e1c3 series 11.4.3 built -in cr oscillation characteristics built - in high - speed cr (v = 1.65 v to 3.6 v, v = 0 v, = 40 10 5 ) parameter symbol conditions value unit remarks min typ max clock frequency ta = 1 to + 105 7.92 8 8.08 after trimming *1 ta = 4 to + 105 7.84 8 8.16 frequency stabilization time s *1: in the case of using the values in cr trimming area of flash memory at shipment for frequency trimming/temperature trimming. *2: this is time from the trim value setting to stable of the frequency of the igh speed clock. after setting the trim value, the period when the frequency stability time passes can use the igh speed clock as a source clock. built - in low - speed cr (v = 1.65 v to 3.6 v, v = 0 v, = 40 10 5 ) parameter symbol conditions value unit remarks min typ max clock frequency f 50 100 150 k
document number: page 58 of 107 s6e1c3 series 11.4.4 operating conditions of main pll ( in the case of using the main clock as the input clock of the pll ) (v = 1.65 v to 3.6 v, v = 0 v, = 40 10 5 ) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time* 1 (lock up time) 50 s pll input clock frequency 8 16 pll multiple rate 5 18 multiple pll macro oscillation clock frequency 75 150 main pll clock frequency* 40 usb clock frequency* 4 8 1 : the wait time is the time it takes for pll oscillation to stabilize. *2: details of the main pll clock (clkpll), refer to " chapter : clock" in "fm0+ family peripheral manual ". *3: for more information about usb clock, see "chapter: usb clock generation" in "fm family peripheral manual communication macro part. 11.4.5 operating conditions of main pll (in the case of using the built -in high - speed cr clock as the input clock of the main pll) (v = 1.65 v to 3.6 v, v = 0 v, = 40 10 5 ) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time* 1 (lock up time) 50 s pll input clock frequency 7.84 8 8.16 pll multiple rate 9 18 multiple pll macro oscillation clock frequency 7 5 150 main pll clock frequency* 40 .8 1 : the wait time is the time it takes for pll oscillation to stabilize. *2: details of the main pll clock (clkpll), refer to " chapter : clock" in "fm0+ family peripheral manual ". note: high speed clock (clkhc) input clock main macro oscillation clock divider main clock (clkpll) n divider main pll connection main clock (clkmo) divider usb clock divider 86forf
document number: page 59 of 107 s6e1c3 series ? for the main pll source clock, i nput the high - speed cr clock (clkhc) whose frequency and temperature have been trimme d. when setting pll multiple rate, please take the accuracy of the built - in h igh - speed c r clock into account and prevent the master clock from exceeding the maximum frequency. 11.4.6 reset input characteristics (v = 1.65 v to 3.6 v, v = 0 v, = 40 10 5 ) parameter symbol pin name conditions value unit remarks min max reset input time initx initx 500 ns 11.4.7 power - on reset timing (v = 1.65 v to 3.6 v, v = 0 v, = 40 10 5 ) parameter symbol pin name value unit remarks min max power supply rising time vccr v ms power supply shut down time 1 ms vcc < 0.2v time until releasing on reset 0.43 3.4 ms 0 . 2 v vdh _ minimum vcc _ minimum internal reset vcc cpu operation start reset active release vccr v v glossary ? vcc_minimum : minimum v of recommended operating conditions ? vd _minimum : minimum detection voltage of low v oltage detection reset " 11.7 voltage ch aracteristics "
document number: page of 107 s6e1c3 series 11.4.8 base timer input timing tim er input timing (v = 1.65 v to 3.6 v, v = 0 v, = 40 10 5 ) parameter symbol pin name conditions value unit remarks min max input pulse width tioan/tiobn (when using as eck, tin) cycp ns trigger input timing (v = 1.65 v to 3.6 v, v = 0 v, = 40 10 5 ) parameter symbol pin name conditions value unit remarks min max input pulse width tioan/tiobn (when using as tgin) cycp ns note: ? t cycp indicates the apb bus clock cycle time. for the number of the apb bus to which the base timer has been connected , see " 8 . block diagram ". t tiwh v v v v v v v v tin tgin
document number: page 61 of 107 s6e1c3 series 11.4.9 csio /spi/uart timing csio (spi = 0, scinv = 0) (v = 1.65 v to 3.6 v, v = 0 v, = 40 10 5 ) parameter symbol pin name conditions v cc < 2.7 v v cc serial clock cycle time scyc master mode 4 cycp 4 cycp ns sck sot delay time slovi ns sin sck setup time ivshi sinx 50 ns sck sin hold time sinx ns serial clock "l" pulse width slave mode cycp 10 cycp 10 ns serial clock "h" pulse width cycp + 10 cycp 10 ns sck sot delay time slove 50 ns sin sck setup time ivshe sinx 10 10 ns sck sin hold time sinx ns sck falling time 5 5 ns sck rising time 5 5 ns notes : ? the above ac characteristics are for clock synchronous mode. ? t cycp represents the apb bus clock cycle time. for the number of the apb bus to which multi - function serial has been connected, see " 8 . block diagram ". ? the characteristics are only applicable when the relocate port numbers are the same. for instance, they are not applicable for the combination of sckx_0 and sotx_1. ? external load capacitance c l = 30 pf
document number: page of 107 s6e1c3 series master mode slave mode scyc v v v v v v v v v t slovi t ivshi t shii sc sot sin t shsl v t f t r v v v v v v v v v v t slove t ivshe t shie sc sot sin
document number: page of 107 s6e1c3 series csio (spi = 0, scinv = 1 ) (v = 1.65 v to 3.6 v, v = 0 v, = 40 10 5 ) parameter symbol pin name conditions v cc < 2.7 v v cc serial clock cycle time scyc master mode 4 cycp 4 cycp ns sck sot delay time shovi ns sin sck setup time ivsli sinx 50 ns sck sin hold time sinx ns serial clock "l" pulse width slave mode cycp 10 cycp 10 ns serial clock "h" pulse width cycp + 10 cycp + 10 ns sck sot delay time shove 50 ns sin sck setup time ivsle sinx 10 10 ns sck sin hold time sinx ns sck falling time 5 5 ns sck rising time 5 5 ns notes : ? the above ac characteristics are for clock synchronous mode. ? t cycp represents the apb bus clock cycle time. for the number of the apb bus to which multi - function serial has been connected, see " 8 . block diagram ". ? the characteristics are only applicable when the relocate port numbers are the same. for instance, they are not applicable for the combination of sckx_0 and sotx_1. ? external load capacitanc e c l = 30 pf
document number: page 64 of 107 s6e1c3 series master mode slave mode scyc v v v v v v v v v t shovi t ivsli t slii sc sot sin t slsh v t f t r v v v v v v v v v v t ivsle t slie sc sot sin shove
document number: page 65 of 107 s6e1c3 series spi (spi = 1, scinv = 0 ) (v = 1.65 v to 3.6 v, v = 0 v, = 40 10 5 ) parameter symbol pin name conditions v cc < 2.7 v v cc serial clock cycle time scyc master mode 4 cycp 4 cycp ns sck sot delay time shovi ns sin sck setup time ivsli sinx 50 ns sck sin hold time sinx ns sot sck delay time sovli cycp cycp ns serial clock "l" pulse width slave mode cycp 10 cycp 10 ns serial clock "h" pulse width cycp + 10 cycp + 10 ns sck sot delay time shove 50 ns sin sck setup time ivsle sinx 10 10 ns sck sin hold time sinx ns sck falling time 5 5 ns rising time 5 5 ns notes : ? the above ac characteristics are for clock synchronous mode. ? t cycp represents the apb bus clock cycle time. for the number of the apb bus to which multi - function serial has been connected, see " 8 . block diagram ". ? the characteristics are only applicable when the reloca te port numbers are the same. for instance, they are not applicable for the combination of sckx_0 and sotx_1. ? external load capacitance c l = 30 pf
document number: page of 107 s6e1c3 series master mode slave mode *: changes when writing to tdr register sovli t scyc t shovi v v v v v v v v v v v t ivsli t slii sc sot sin t r t slsh t shsl t shove v v v v v v * v v v v v v v t ivsle t slie sc sot sin
document number: page 67 of 107 s6e1c3 series spi (spi = 1, scinv = 1 ) (v = 1.65 v to 3.6 v, v = v, = 40 10 5 ) parameter symbol pin name conditions v cc < 2.7 v v cc serial clock cycle time scyc master mode 4 cycp 4 cycp ns sck sot delay time slovi ns sin sck setup time ivshi sinx 50 ns sck sin hold time sinx ns sot sck delay time sovhi cycp cycp ns serial clock "l" pulse width slave mode cycp 10 cycp 10 ns serial clock "h" pulse width cycp + 10 cycp + 10 ns sck sot delay time slove 50 ns sin sck setup time ivshe sinx 10 10 ns sck sin hold time sinx ns sck falling time 5 5 ns sck rising time 5 5 ns notes : ? the above ac characteristics are for clock synchronous mode. ? t cycp represents the apb bus clock cycle time. for the number of the apb bus to which multi - function serial has been connected, see " 8 . block diagram ". ? the characteristics are only applicable when the relocate port numbers are the same. for instance, they are not applicable for the combination of sckx_0 and sotx_1. ? external load capacitance c l = 30 pf
document number: page 68 of 107 s6e1c3 series master mode slave mode t scyc slovi 9 ol 9 oh 9 oh 9 oh 9 o l 9 oh 9 o l 9 ih 9 i l 9 ih 9 i l t ,96, t shii t 629, sc sot 6,1 t shsl t r t slsh t f t slove v v v v v v v v v v v v v t ivshe t shie sc sot sin
document number: page 69 of 107 s6e1c3 series when using csio/spi chip select (scinv=0 , cslvl=1 ) (v = 1.65 v to 3.6 v, v = 0 v, t = 40 10 5 ) parameter symbol conditions v cc < 2.7 v v cc 2.7 v unit min max min max scs setup time master mode (*1) 5 (*1)+0 (*1) 5 (*1)+0 ns hold time (*2)+0 (*2)+ 5 (*2)+0 (*2)+ 5 ns deselect time (*3) 5 (*3)+ 5 (*3) 5 (*3)+ 5 ns setup time slave mode cycp cycp ns hold time ns deselect time cycp cycp ns delay time 55 40 ns delay time ns *1 : cssu bit value serial chip select timing operating clock cycle : cshd bit value serial chip select timing operating clock cycle : csds bit value serial chip select timing operating clock cycle irrespectiv e of setting, 5 cycp or more are required fo r the period the time when the s erial hip s elect pin becomes inactive to the time when the s erial hip s elect pin becomes a ctive again. notes : ? t cycp indicates the apb bus clock cycle time. for information a bout the apb bus number which multi - function serial is connected to, see " 8 . block diagram ". ? for information a bout cssu, cshd, csds, serial chip select timing operating clock, se e "fm0+ family peripheral manual ". ? these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and s csi x_1 is not guaranteed. ? when the external load capacitance c l = 30 p f.
document number: page 70 of 107 s6e1c3 series master mode slave mode t cssi t cshi t csdi t d s e t csse t cshe t csde t dee scso sck sot (spi=0) sot (spi=1) scsi sck sot (spi=0) sot (spi=1)
document number: page 71 of 107 s6e1c3 series when using csio/spi chip select (scinv= 1, cslvl=1 ) (v = 1.65 v to 3.6 v, v = 0 v, t = 40 10 5 ) parameter symbol conditions v cc < 2.7 v v cc 2.7 v unit min max min max scs setup time master mode (*1) 5 (*1)+0 (*1) 5 (*1)+0 ns hold time (*2)+0 (*2)+ 5 (*2)+0 (*2)+ 5 ns deselect time (*3) 5 (*3)+ 5 (*3) 5 (*3)+ 5 ns setup time slave mode cycp cycp ns hold time ns deselect time cycp cycp ns delay time 55 40 ns delay time ns *1 : cssu bit value serial chip select timing operating clock cycle : cshd bit value serial chip select timing operating clock cycle : csds bit value serial chip select timing operating clock cycle irrespectiv e of setting, 5 cycp or more are required fo r the period the time when the s erial hip s elect pin becomes inactive to the time when the s erial hip s elect pin becomes active again. notes : ? t cycp indicates the apb bus clock cycle time. for information a bout the apb bus number which multi - function serial is connected to, see " 8 . block diagram ". ? for information a bout cssu, cshd, csds, serial chip sel ect timing operating clock, see "fm0+ family peripheral manual ". ? these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and s csi x_1 is not guaranteed. ? when the external load capacitance c l = 30 p f.
document number: page 72 of 107 s6e1c3 series master mode slave mode t cssi t cshi t csdi t d s e t csse t cshe t csde t dee scso sck sot (spi=0) sot (spi=1) scsi sck sot (spi=0) sot (spi=1)
document number: page 73 of 107 s6e1c3 series when using csio/spi chip select (scinv= 0, cslvl=0 ) (v = 1.65 v to 3.6 v, v = 0 v, t = 40 10 5 ) parameter symbol conditions v cc < 2.7 v v cc 2.7 v unit min max min max scs setup time master mode (*1) 5 (*1)+0 (*1) 5 (*1)+0 ns hold time (*2)+0 (*2)+ 5 (*2)+0 (*2)+ 5 ns deselect time (*3) 5 (*3)+ 5 (*3) 5 (*3)+ 5 ns setup time slave mode cycp cycp ns hold time ns deselect time cycp cycp ns delay time 55 40 ns delay time ns *1 : cssu bit value serial chip select timing operating clock cycle : cshd bit value serial chip select timing operating clock cycle : csds bit value serial chip select timing operating clock cycle irrespectiv e of setting, 5 cycp or more are required fo r the period the time when the s erial hip s elect pin becomes inactive to the time when the s erial hip s elect pin becomes active again. notes : ? t cycp indicates the apb bus clock cycle time. for information a bout the apb bus number which multi - function ser ial is connected to, see " 8 . block diagram ". ? for information a bout cssu, c shd, csds, serial chip select timing operating clock, see "fm0+ family peripheral manual ". ? these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and s csi x_1 is not guaranteed. ? when the external load capacitance c l = 30 p f.
document number: page 74 of 107 s6e1c3 series master mode slave mode t cssi t cshi t csdi t d s e t csse t cshe t csde t dee scso sck sot (spi=0) sot (spi=1) scsi sck sot (spi=0) sot (spi=1)
document number: page 75 of 107 s6e1c3 series when using csio/spi chip select (scinv= 1, cslvl=0 ) (v = 1.65 v to 3.6 v, v = 0 v, t = 40 10 5 ) parameter symbol conditions v cc < 2.7 v v cc 2.7 v unit min max min max scs setup time master mode (*1) 5 (*1)+0 (*1) 5 (*1)+0 ns hold time (*2)+0 (*2)+ 5 (*2)+0 (*2)+ 5 ns deselect time (*3) 5 (*3)+ 5 (*3) 5 (*3)+ 5 ns setup time slave mode cycp cycp ns hold time ns deselect time cycp cycp ns delay time 55 40 ns delay time ns *1 : cssu bit value serial chip select timing operating clock cycle : cshd bit value serial chip select timing operating clock cycle : csds bit value serial chip select timing operating clock cycle irrespectiv e of setting, 5 cycp or more are required fo r the period the time when the s erial hip s elect pin becomes inactive to the time when the s erial hip s elect pin becomes active again. notes : ? t cycp indicates the apb bus clock cycle time. for information a bout the apb bus number which multi - function serial is connected to, see " 8 . block diagram ". ? for information a bout cssu, cshd, csds, serial chip select timing operating clock, see "fm0+ family peripheral manual ". ? these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and s csi x_1 is n ot guaranteed. ? when the external load capacitance c l = 30 p f.
document number: page 76 of 107 s6e1c3 series master mode slave mode t cssi t cshi t csdi t d s e t csse t cshe t csde t dee scso sck sot (spi=0) sot (spi=1) scsi sck sot (spi=0) sot (spi=1)
document number: page 77 of 107 s6e1c3 series uart external clock input (ext = 1 ) (v = 1.65 v to 3.6 v, v = v, = 40 10 5 ) parameter symbol conditions value unit remarks min max serial clock l pulse width = pf cycp 10 ns serial clock h pulse width cycp 10 ns sck falling time 5 ns sck rising time 5 ns t shsl v v v v v t r t f t slsh s c
document number: page 78 of 107 s6e1c3 series 11.4.10 external input timing (v = 1.65 v to 3.6 v, v = v, = 40 10 5 ) parameter symbol pin name conditions value unit remarks min max input pulse width inh, inl cycp 1 ns a/d converter trigger input int to int08 int12, int13, int 1 5 , nmix cycp 100 1 ns external interrupt nmi 500 ns wkupx *4 500 ns deep standby wake up *1: cycp represents the apb bus clock cycle time for the number of the apb bus to which the multi function timer is connected and that of the apb bus to which the external interrupt controller is connected, see " 8 block diagram ". : run mode and sleep mode : timer mode rtc mode and stop mode 4 : deep standby rtc mode and deep standby stop mode t inh in v v v v
document number: page 79 of 107 s6e1c3 series 11.4.11 i 2 c timing / i2c slave timing (v = 1.65 v to 3.6 v, v = v, = 40 10 5 ) parameter symbo l conditions standard - mode fast - mode unit remarks min max min max scl (si2cscl) clock frequency = pf, = (vp/i ) 1 100 400 khz (repeated) start condition hold time (si2csda) scl (si2cscl) 4.0 s scl (si2cscl) clock l width 4.7 1.3 s (si2cscl) clock h width 4.0 s (repeated) start setup time (si2cscl) sda (si2csda) susta 4.7 s data hold time (si2cscl) sda (si2csda) 3.45* 0.9* s data setup time (si2csda) scl (si2cscl) sudat 250 100 ns stop condition setup time (si2cscl) sda (si2csda) susto 4.0 s bus free time between stop condition and start condition buf 4.7 1.3 s noise filter cycp 4 cycp 4 ns e xcept i2c slave *1: r represent s the pull up resistance of the scl and sda lines and c the load capacitance of the scl and sda lines. v represents the power supply voltage of the pull up resistance and i the v guaranteed current. *2: the maximum t must satisfy at least the condition that the period during which the device is holding the scl signal at l (t ) does not e xtend. *3: fast mode c bus device can be used in a tandard mode i c bus system , provided that t he condition of sudat 250 ns is fulfilled. *4: cycp represents the apb bus clock cycle time. for the number of the apb bus to which the i c is connected, see " 8 block diagram ". to use tandard mode, set the apb bus c lock at 2 mhz or more. to use fast mode, set the apb bus clock at 8 mhz or more. t low t hdsta t hddat t high t sudat susta susto buf
document number: page 80 of 107 s6e1c3 series 11.4.12 i 2 s timing ( mfs - i2s timing) master mode timing (v = 1.65 v to 3.6 v, v = 0 v, = 40 10 5 ) parameter symbo l pin name conditions v cc < 2.7 v v cc max frequency (*1) = pf 6.144 6.144 s clock cycle time (*1) icyc 4 cycp 4 cycp ns s clock duty cycle ? 45% 55% 45% 55% delay time ns delay time ns setup time 50 ns hold time ns falling time 5 5 ns rising time 5 5 ns *1: i 2 s clock should meet the multiple of pclk(t icyc ) and the frequency less than f meantime the detail information p lease refer to chapter 2 s of communication macro part of peripheral manual and v v v v v v v v v v
document number: page 81 of 107 s6e1c3 series m i2smck input characteristics (v = 1.65 v to 3.6 v, v = 0 v, t = 40 105 ) parameter symbol pin name conditions value unit remarks min max input frequency f 12.288 input clock cycle cylhs 81.3 ns input clock pulse width /t cylhs /t cylhs 45 55 % when using external clock input clock rise time and fall time 5 ns when using external clock m i2smck output characteristics (v = 1.65 v to 3.6 v, v = 0 v, t = 40 105 ) parameter symbol pin name conditions value unit remarks min max out put frequency f 25 v 2.7 v v 2.7 v
document number: page 82 of 107 s6e1c3 series 11.4.13 smart card interface ch aracteristics (v = 1.65 v to 3.6 v, v = 0 v, t = 40 10 5 ) parameter symbol pin name conditions value unit remarks min max output rising time icx_ vcc icx_rst _clk icx_data = pf 4 ns output falling time 4 ns output clock frequency f _clk duty cycle ? 45% 55% ? external pull up resistor (20 k 50 k ) must be applied to icx_cin pin when its used as smart card reader function.
document number: page 83 of 107 s6e1c3 series 11.4.14 sw -dp timing (v = 1.65 v to 3.6 v, v = v, = 40 10 5 ) parameter symbol pin name conditions value unit remarks min max swdio setup time 15 ns swdio hold time 15 ns swdio delay time 45 ns note: ? external load capacitance c l = 30 pf v v v v v v v v jtags jtagd jtagh (when input) (when output)
document number: page 84 of 107 s6e1c3 series 11.5 12- bit a/d converter electrical characteristics of a/d c onverter ( preliminary values ) (v = 1.65 v to 3.6 v, v = v, = 40c to 10 5 c) parameter symbol pin name value unit remarks min typ max resolution 12 integral nonl inearity 4.5 4.5 differential non linearity 2.5 + 2.5 zero transition voltage v an 15 15 mv full scale transition voltage v an avrh 15 avrh 15 mv conversion time 1 1 s v 2.7 v 4.0 1.8 v 2.7 v 10 1.65 v 1.8 v sampling time ts 10 s v 2.7 v 1.2 1.8 v 2.7 v 1.65 v 1.8 v compare clock cycle tcck 5 1000 ns v 2.7 v 1.8 v 2.7 v 500 1.65 v 1.8 v state transition time to operation permission ts t t 1.0 s analog input capacity ain 7.5 pf analog input resistance ain k v 2.7 v 5. 5 1.8 v 2.7 v 10.5 1.65 v 1.8 v interchannel disparity 4 analog port input leak current an 5 analog input voltage an v avrh v reference voltage avrh 2.7 v v vcc 2.7v v vcc < 2.7v avrl v v v *1: the c onversion time is the value of sampling time ( ) + compare time ( ). the minimum conversion time is computed according to the following conditions: v 7 v sampling time = s , compare time = 0.7 s 1.8 v 2.7 v sampling time = 1.2 s , compare time = 2.8 s 1.65 v 1.8 v sampling time = s , compare time = 7.0 s ensure that the conversion time satisfies the specifications of the sampling time ( ) and compare clock cycle ( ). details of the settings of the sampling time and compare clock cycle, refer to " chapter : a/d converter " in " family peripheral manual analog macro part ". the register setting s of the / onverter are reflected in the operation according to the apb bus clock timing. for the number of the apb bus to which the a/d converter is connected, see " 8 block diagram ". the base clock (hclk) is used to generate the sampling time and the compare clock cycle. *2: the required sampling time varies according to the external impedance. set a sampling time that satisfies ( equation 1). *3: the compare time ( ) is the result of ( equation 2).
document number: page 85 of 107 s6e1c3 series (equation 1) ( ain ) ain 9 : sampling time n : nput resistance of a/d = k with 2.7 vcc nput resistance of a/d = 5. 5 k with 1.8 vcc 2.7 nput resistance of a/d = 10.5 k with 1.65 vcc 1.8 ain : nput capacit ance of a/d = 7.5 pf with 1.65 vcc : output impedance of external circuit (equation 2) = 14 : compare time : compare clock cycle r ain c omparator an analog input pin s ain analog signal source
document number: page 86 of 107 s6e1c3 series definition s of 1 2 - bit a/d converter terms ? resolution : analog variation that is recognized by an a/d converter. ? integral nonl inearity : deviation of the line between the zero transition point (0b000000000000 0b000000000001) and the full scale transition point (0b111111111110 0b111111111111) from the actual conversion characteristics. ? differential non linearity : deviation from the ideal value of the input voltage that is required to change the output code by 1 lsb. integral nonl inearity of digital output n = v nt {1lsb (n 1) + v 1lsb differential nonlinearity of digital output n = v (n + 1) t v nt 1 [lsb] 1lsb 1lsb = v v 4094 n : a/d converter digital output value. v : voltage at whi ch the digital output ch anges from 0x000 to 0x001. v : voltage at whi ch the digital output ch anges from 0xffe to 0xfff. v nt : voltage at whi ch the digital output ch anges from 0x(n ? 1) to 0xn. integral nonl inearity differential non linearity digital output digital output actual conversion characteristics actual conversion characteristics ideal characteristics (actually measured value) actual conversion characteristics actual conversion characteristics (actually measured value) (actually measured value) ideal characteristics (actually measured value) analog input analog input (actually measured value) 0x001 0x004 v avrh v avrh 0x(n 2) 0x(n 1) 0x(n+1) 0xn {1 lsb(n 1) + v v nt v v v nt v (n+1)t
document number: page 87 of 107 s6e1c3 series 11.6 usb ch aracteristics (v = v to 3.6 v, v = v, = 40 105 ) parameter symbol pin name conditions value unit remarks min max input characteristics input h level voltage v udp0, udm0 v v *1 input l level voltage v v 0.8 v *1 differential input sensitivity v v differential common mode range v 0.8 2.5 v output characteristic output h level voltage v external pull down resistance = 15 k? 2.8 v output l level voltage v external pull up resistance = 1.5 k? v crossover voltage v 1.3 v *4 rising time full speed 4 ns *5 falling time full speed 4 ns *5 rising/falling time matching full speed 90 111.11 % *5 output impedance drv full speed 28 44 ? rising time speed 75 ns *7 falling time speed 75 ns *7 rising/falling time matching speed 80 125 % *7 *1 : the switching threshold voltage of single end receiver of usb i/o buffer is set as within v (max) = 0.8 v, vih(min) = 2.0 v (ttl input standard). there are some hysteresis to lower noise sensitivity. *2 : use differential receiver to receive usb differential data signal. differential receiver has 200 mv of differential input sensitivity when the differential data input is with in 0.8 v to 2.5 v to the local ground reference level. above voltage range is the common mode input voltage range. *3 : the output drive capability of the driver is below 0.3 v at low state (v ) (to 3.6 v and 1.5 k? load), and 2.8 v or above 0.8 2.5 rpprqprghlqsxwyrowdh9 0lqlpxpgliihuhqwldolqsxwvhqvlwlylw 9 0. 2 1.0
document number: page 88 of 107 s6e1c3 series (to the vss and 1.5 k? load) at high state (v ) *4 : the cross voltage of the external differential output signal (d+ / d ) of us b i/o buffer is within 1.3 v to 2.0 v. *5 : the indicate rising time (trise) and falling time (tfall) of the full speed differential data signal. they are defined by the time between 10% and 90% of the output signal voltage. for full speed buffer, tr/tf ratio is regulated as within 10% to minimize rfi emission. *6 : usb full speed connection is performed via twist pair cable shield with 90 ? 15% characteristic impedance (differential mode). usb standard defines that output impedance of usb driver must be in range from 28? to 44?. so, discrete series resistor (rs) addition is defined in order to satisfy the above definition and keep balance. when using this usb i/o, use it with 25 ? to 33 ? (recommendation value : 27 ?) series resistor rs. v specified range max 2.0v d+ min 1.3v d - trise rising time 90% d+ d - 10% 90% 10% tfall falling time tx d - rs=27 ? rs=27 ? =50 pf =50 pf full speed buffer state enable
document number: page 89 of 107 s6e1c3 series *7 : they indicate rising time (trise) and falling time (tfall) of the low speed differential data signal. they are defined by the time between 10% and 90% of the output signal voltage. speed load (com p liance load) for condition of external load. tx d - rs rs full speed buffer state enable 28 ? to 44 ? equivalent impedance 28 ? to 44 ? equivalent impedance rs series resistor 25 ? to 30 ? series resistor of 27 ? (recommendation value) must be added. and, use resistance with an uncertainty of 5% by e24 sequence. mount it as external resistance. trise rising ti me 90% d+ d - 10% 90% 10% tfall falling time
document number: page 90 of 107 s6e1c3 series ? speed load (upstream port load) reference 1 ? speed load (downstream port load) reference 2 tx d tx d - rs=27 ? rs=27 ? =50 pf to 150 pf speed buffer state enable rpd =50 pf to 150 pf rpd rpd=15 k? tx d - rs=27 ? rs=27 ? =200 pf to 600 pf speed buffer state enable c l =50 pf to 150 pf rpu=1.5 k? vterm=3.6 v vterm
document number: page 91 of 107 s6e1c3 series ? speed load (compliance load) tx d tx d - rs=27 ? rs=27 ? =200 pf to 450 pf speed buffer state enable =200 pf to 450 pf
document number: page 92 of 107 s6e1c3 series 11.7 low - voltage d etection ch aracteristics 11.7.1 l ow - voltage d etection r eset ( = 40 105 ) parameter symbol conditions value unit remarks min typ max detected voltage vdl fixed *1 1.38 1.50 1.60 v when voltage drops released voltage vdh 1.43 1.55 1.65 v when voltage rises lvd stabilization wait time lvdw 8160 cycp s lvd detection delay time lvd s *1: the value of voltage detection reset is always fixed. *2: cycp indicates the apb 1 bus clock cycle time.
document number: page 93 of 107 s6e1c3 series 11.7.2 l ow - voltage d etection interrupt ( = 40 105 ) parameter symbo l conditions value uni t remarks min typ max detected voltage vdl svhi = 00100 1.56 1.70 1.84 v when voltage drops released voltage vdh 1.61 1.75 1.89 v when voltage rises detected voltage vdl svhi = 00101 1.61 1.75 1.89 v when voltage drops released voltage vdh 1.66 1.80 1.94 v when voltage rises detected voltage vdl svhi = 00110 1.66 1.80 1.94 v when voltage drops released voltage vdh 1.70 1.85 v when voltage rises detected voltage vdl svhi = 00111 1.70 1.85 v when voltage drops released voltage vdh 1.75 1.90 2.05 v when voltage rises detected voltage vdl svhi = 01000 1.75 1.90 2.05 v when voltage drops released voltage vdh 1.79 1.95 2.11 v when voltage rises detected voltage vdl svhi = 01001 1.79 1.95 2.11 v when voltage drops released voltage vdh 1.84 2.16 v when voltage rises detected voltage vdl svhi = 01010 1.84 2.16 v when voltage drops released voltage vdh 1.89 2.05 2.21 v when voltage rises detected voltage vdl svhi = 01011 1.89 2.05 2.21 v when voltage drops released voltage vdh 1.93 2.10 2.27 v when voltage rises detected voltage vdl svhi = 01100 2.50 2.70 v when voltage drops released voltage vdh 2.39 2.81 v when voltage rises detected voltage vdl svhi = 01101 2.39 2.81 v when voltage drops released voltage vdh 2.48 2.70 2.92 v when voltage rises detected voltage vdl svhi = 01110 2.48 2.70 2.92 v when voltage drops released voltage vdh 2.58 2.80 v when voltage rises detected voltage vdl svhi = 01111 2.58 2.80 v when voltage drops released voltage vdh 2.67 2.90 3.13 v when voltage rises detected voltage vdl svhi = 10000 2.67 2.90 3.13 v when voltage drops released voltage vdh 2.76 3.24 v when voltage rises detected voltage vdl svhi = 10001 2.76 3.24 v when voltage drops released voltage vdh 2.85 3.10 3.35 v when voltage rises detected voltage vdl svhi = 10010 2.85 3.10 3.35 v when voltage drops released voltage vdh 2.94 3.46 v when voltage rises detected voltage vdl svhi = 10011 2.94 3.46 v when voltage drops released voltage vdh 3.04 3.56 v when voltage rises lvd stabilization wait time lvdw 8160 cycp s lvd detection delay time lvd s *: cycp represents the 1 bus clock cycle time.
document number: page 94 of 107 s6e1c3 series 11.8 flash memory write/erase characteristics ( v = 1.65 v to 3.6 v = 40 10 5 ) parameter value unit remarks min typ max sector erase time large s 1.1 2.7 s the sector erase time includes the time of writing prior to internal erase. small sector 0.9 half word (16 bit) time 528 s the halfword (16 bit) write time excludes t he system level overhead. chip erase time 4.5 11.7 s the chip erase time includes the time of writing prior to internal erase. *: the typical value is immediately after shipment , the maxim u m value is guarantee value under 10,000 cycle of erase/write w rite / erase cycle and data hold time w rite / erase cycle data hold time ( year ) remarks 1,000 10,000 10* *: this value comes from the technology qualification (using arrhenius equation to translate high temperature acceleration test result into average temperature value at + 85c).
document number: page 95 of 107 s6e1c3 series 11.9 return time from low - power consumption mode 11.9.1 return f actor: interrupt/wkup the return time from low power consumption mode is indicated as follows. it is from eceiving the return factor to starting the program operation. return c ount t ime ( v = 1.65 v to 3.6 v = 40 10 5 ) parameter symbol value unit remarks current mode mode to return typ max *1 sleep mode ach run modes icnt 4*hclk s when high speed cr is enabled timer mode high s peed cr run mode main run mode pll run mode 12*hclk 13*hclk s when high speed cr is enabled speed cr run mode sub run mode 34+12*hclk 72+13*hclk s stop mode high s peed cr run mode speed cr run mode 34+12*hclk 72+13*hclk s main run mode sub run mode pll run mode 34+12*hclk 72+13*hclk s rtc mode high s peed cr run mode speed cr run mode sub run mode 34+12*hclk 72+13*hclk s main run mode pll run mode 34+12*hclk 72+13*hclk s deep standby rtc mode deep standby stop mode high s peed cr run mode 43 281 s 1 : the maximum value depends on the condition of environment *2: : oscillator stabilization time. operation example of return from l ow - p ower consumption mode (by external interrupt *) external interrupt icnt interrupt factor accept cpu operation start interrupt factor clear by cpu *: external interrupt is set to detecting fall edge.
document number: page 96 of 107 s6e1c3 series operation example of return from low - power consumption mode (by internal resource interrupt *) internal resource interrupt icnt interrupt factor accept cpu operation start interrupt factor clear by cpu *: internal resource interrupt is not included in return factor by the kind of low power consumption mode. notes: ? the return factor is different in each low - power consumption modes. see "chapter: low power consumption mode" and "operations of standby modes" in fm0+ family peripheral manual . ? when interrupt recoveries, the operation mode that cpu recoveries depends on the state before the low - power consumption mode transition. see " chap ter : low power consumption mode" in "fm0+ family peripheral manual ".
document number: page 97 of 107 s6e1c3 series 11.9.2 return f actor: reset the return time from low power consumption mode is indicated as follows. it is from releasing reset to starting the program operation. return c ount t ime ( v = 1.65 v to 3.6 v = 40 10 5 ) parameter symbol value unit remarks current mode mode to return typ max* high speed cr sleep mode main sleep mode pll sleep mode high speed run mode rcnt s when high speed cr is enabled speed sleep mode 50 106 s when high speed cr is enabled sub sleep mode 112 137 s when high speed cr is enabled high speed cr timer mode main timer mode pll timer mode s when high speed cr is enabled speed cr timer mode 87 159 s sub timer mode 148 209 s stop mode rtc mode 45 68 s deep standby rtc mode deep standby stop mode 43 281 s *: the maximum value depends on the accuracy of built operation example of return from l ow - p ower consumption mode (by initx) initx rcnt internal reset cpu operation start reset active release
document number: page 98 of 107 s6e1c3 series operation example of return from low power consumption mode (by internal resource reset *) internal resource reset rcnt internal reset cpu operation start reset active release *: internal resource reset is not included in return factor by the kind of low power consumption mode. notes: ? the return factor is different in each low - power consumption modes. see "chapter: low power consumption mode" and "operations of standby modes" in fm0+ family peripheral manual . ? when interrupt recoveries, the operation mode that cpu recoveri es depends on the state before the low - power consumption mode transition. see " chapter : low power consumption mode" in "fm0+ family peripheral manual ". ? the time during the power - on reset/low - voltage det ection reset is excluded. see " 11.4.7 power - on reset timing in 11.4 ac characteristics in 11 . electrical characteristics " for the detail on the time during the power - on reset/low - voltage detection reset. ? when in recovery from reset, cpu changes to the high - speed cr run mode. when using the main clock or the pll clock, it is necessary to add the main clock oscillation stabilization wait time or the main pll clock stabilization wait time. ? the internal resource reset means the watchdog reset and the csv reset.
document number: page 99 of 107 s6e1c3 series 12. ordering information part number on - chip flash memory [kbyte] on - chip sram [kbyte] package packing S6E1C32D0AGV20000 128 16 plastic ? (0.5 mm pitch) 64 pin s ( lqd064 ) tray s6e1c31d0agv20000 64 12 s6e1c32c0agv20000 128 16 plastic ? (0. 50 mm pitch) 48 pin s ( lqa048 ) tray s6e1c31c0agv20000 64 12 s6e1c32b0agp20000 128 16 plastic ? (0. 8 mm pitch) pin s ( ) tray s6e1c31b0agp20000 64 12 s6e1c32d0agn20000 128 16 plastic qfn64 (0.5 mm pitch) 64 pin s ( wns064 ) tray s6e1c31d0agn20000 64 12 s6e1c32c0agn20000 128 16 plastic qfn48 (0.5 mm pitch) 48 pin s ( wny048 ) tray s6e1c31c0agn20000 64 12 s6e1c32b0agn20000 128 16 plastic qfn32 (0.5 mm pitch) pin s ( wnu032 ) tray s6e1c31b0agn20000 64 12 (tbd) 128 16 (tbd) (tbd)
document number: page 100 of 107 s6e1c3 series 13. package dimensions
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document number: page 106 of 107 s6e1c3 series document history document title: s6e1c3 series 32 - bit arm ? cortex ? - m0+ fm0+ microcontroller document number: 002- 00233 revision ecn orig. of change submission date description of change ** 4896074 08/ 31 /2015 new spec. 4955136 10/ 9 /2015 ac/dc characteristics updated. typo fixed in list of pin functions 5158709 yukt / 4 /2016 added the frequency value of ta = 1 to + 105 11.4.3 built cr oscillation characteristics added the remark of vcc < 0.2v on 11.4.7 power reset timing added the measure condition(*9) of icc on 11.3.1 current rating changed the package outlines to cypress format on 13. package dimensions changed the package codes to cypress codes on 3. pin assignment and 12. ordering information
document number: march 4, 2016 page 107 of 107 s6e1c3 series sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. to find the office closest to you, visit us at cypress locations products arm ? cortex ? microcontrollers cypress.com/a rm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface lighting & power control cypress.com/powerpsoc memory cypress.com/memory cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/ usb wireless/rf cypress.com/wireless psoc? solutions cypress.co m/psoc psoc 1 psoc 4 psoc 5lp cypress developer community community forums blogs video training technical support cypress.com/support arm and cortex are the registered trademarks of arm limited in the eu and other countries. ? cypress semiconductor corporation 2015 2016. this document is the property of cypress semiconductor corporation and its subsidiaries, including spansion llc ("cypre ss"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellectual property laws and treaties o f the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a written agreement with cyp ress governing the use of the software, then cypress hereby grants you under its copyright rights in the software, a personal, non exclusive, nontransferable license (without the right to sublicense) (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to di stribute the software in binary code form externally to end users (either directly or indirectly through resellers and distrib utors), solely for use on cypress hardware product units. cypress also grants you a personal, non exclusive, nontransferable, license (without the right to sublicense) under those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely to the minimum extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. any ot her use, reproduction, modification , translation, or compilation of the software is prohibited. cypress makes no warranty of any kind, express or implied, with regard to this document or any software, including, but not l warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes to this document without further notice. cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. any informat ion provi ded in this document, including any sample design information or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any appl ication made of this information and any resulting product. cypress products are not designed, intended, or authorized for use as cri tical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollu hazardous substances management, or other uses where the failure of the device or system could cause personal inju ry, death, or property damage ("unintended uses"). a critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or sys tem, or to affect its safety or effectiveness. cypre ss is not liable, in whole or in part, and company shall and hereby does release cypress from any claim, damage, or other liability arising from or rela ted to all unintended uses of cypress products. company shall indemnify and hold cypress harmless from a nd against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereo f, psoc, capsense, ez usb, f ram, and traveo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brands may be claimed as property o f their respective owners.

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